[people/ms/u-boot.git] / include / configs / corvus.h

/*
 * Common board functions for siemens AT91SAM9G45 based boards
 * (C) Copyright 2013 Siemens AG
 *
 * Based on:
 * U-Boot file: include/configs/at91sam9m10g45ek.h
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/hardware.h>
#include <linux/sizes.h>

/*
 * Warning: changing CONFIG_SYS_TEXT_BASE requires
 * adapting the initial boot program.
 * Since the linker has to swallow that define, we must use a pure
 * hex number here!
 */

#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY

/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */

/* serial console */
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS

/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE		0x08000000

#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
#endif

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_AT91_WANTS_COMMON_PHY

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS

/* DFU class support */
#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT	25000

#define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6

/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_OFFSET_REDUND	0x180000
#define CONFIG_ENV_SIZE			SZ_128K

#define CONFIG_BOOTCOMMAND						\
	"nand read 0x70000000 0x200000 0x300000;"			\
	"bootm 0x70000000"

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
				SZ_4M, 0x1000)

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		(12 * SZ_1K)
#define CONFIG_SPL_STACK		(SZ_16K)

#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE		(SZ_2K)

#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

#define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
#define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
					  48, 49, 50, 51, 52, 53, 54, 55, \
					  56, 57, 58, 59, 60, 61, 62, 63, }

#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK		132096000
#define AT91_PLL_LOCK_TIMEOUT		1000000
#define CONFIG_SYS_AT91_PLLA		0x20c73f03
#define CONFIG_SYS_MCKR			0x1301
#define CONFIG_SYS_MCKR_CSS		0x1302

#endif
Commit	Line	Data
b89ac72a HS	1	/*
	2	* Common board functions for siemens AT91SAM9G45 based boards
	3	* (C) Copyright 2013 Siemens AG
	4	*
	5	* Based on:
	6	* U-Boot file: include/configs/at91sam9m10g45ek.h
	7	* (C) Copyright 2007-2008
	8	* Stelian Pop <stelian@popies.net>
	9	* Lead Tech Design <www.leadtechdesign.com>
	10	*
	11	* SPDX-License-Identifier: GPL-2.0+
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	#include <asm/hardware.h>
fd45a0d1	18	#include <linux/sizes.h>
b89ac72a	19
b89ac72a HS	20	/*
	21	* Warning: changing CONFIG_SYS_TEXT_BASE requires
	22	* adapting the initial boot program.
	23	* Since the linker has to swallow that define, we must use a pure
	24	* hex number here!
	25	*/
	26
b89ac72a HS	27	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
	28
	29	/* ARM asynchronous clock */
	30	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
	31	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
b89ac72a	32
b89ac72a HS	33	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	34	#define CONFIG_SETUP_MEMORY_TAGS
	35	#define CONFIG_INITRD_TAG
289f979c	36	#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
b89ac72a	37
b89ac72a HS	38	/* general purpose I/O */
	39	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
	40	#define CONFIG_AT91_GPIO
	41	#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
	42
	43	/* serial console */
b89ac72a HS	44	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	45	#define CONFIG_USART_ID ATMEL_ID_SYS
	46
	47	/* LED */
	48	#define CONFIG_AT91_LED
	49	#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
	50	#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
	51
b89ac72a HS	52
	53	/*
	54	* BOOTP options
	55	*/
	56	#define CONFIG_BOOTP_BOOTFILESIZE
b89ac72a	57
b89ac72a HS	58	/* SDRAM */
	59	#define CONFIG_NR_DRAM_BANKS 1
	60	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
	61	#define CONFIG_SYS_SDRAM_SIZE 0x08000000
	62
	63	#define CONFIG_SYS_INIT_SP_ADDR \
72fa5893	64	(CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
b89ac72a	65
b89ac72a HS	66	/* NAND flash */
	67	#ifdef CONFIG_CMD_NAND
	68	#define CONFIG_NAND_ATMEL
	69	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	70	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	71	#define CONFIG_SYS_NAND_DBW_8
	72	/* our ALE is AD21 */
	73	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	74	/* our CLE is AD22 */
	75	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	76	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
a5f8ccae	77	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
b89ac72a HS	78	#endif
	79
	80	/* Ethernet */
	81	#define CONFIG_MACB
	82	#define CONFIG_RMII
	83	#define CONFIG_NET_RETRY_COUNT 20
	84	#define CONFIG_AT91_WANTS_COMMON_PHY
	85
e11793bc HS	86	#define CONFIG_MTD_DEVICE
	87	#define CONFIG_MTD_PARTITIONS
	88
e11793bc	89	/* DFU class support */
e11793bc HS	90	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
	91	#define DFU_MANIFEST_POLL_TIMEOUT 25000
	92
e11793bc	93	#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
b89ac72a HS	94
b89ac72a HS	95	/* bootstrap + u-boot + env in nandflash */
b89ac72a HS	96	#define CONFIG_ENV_OFFSET 0x100000
b89ac72a HS	97	#define CONFIG_ENV_OFFSET_REDUND 0x180000
fd45a0d1	98	#define CONFIG_ENV_SIZE SZ_128K
b89ac72a HS	99
	100	#define CONFIG_BOOTCOMMAND \
	101	"nand read 0x70000000 0x200000 0x300000;" \
	102	"bootm 0x70000000"
b89ac72a	103
b89ac72a HS	104	/*
	105	* Size of malloc() pool
	106	*/
	107	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
fd45a0d1 HS	108	SZ_4M, 0x1000)
fd45a0d1 HS	109
5b15fd98	110	/* Defines for SPL */
5b15fd98	111	#define CONFIG_SPL_TEXT_BASE 0x300000
fd45a0d1 HS	112	#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
fd45a0d1 HS	113	#define CONFIG_SPL_STACK (SZ_16K)
5b15fd98 HS	114
5b15fd98 HS	115	#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
fd45a0d1	116	#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
5b15fd98	117
5b15fd98 HS	118	#define CONFIG_SPL_NAND_DRIVERS
	119	#define CONFIG_SPL_NAND_BASE
	120	#define CONFIG_SPL_NAND_ECC
	121	#define CONFIG_SPL_NAND_RAW_ONLY
	122	#define CONFIG_SPL_NAND_SOFTECC
	123	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
	124	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	125	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	126	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	127	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	128
fd45a0d1 HS	129	#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
fd45a0d1 HS	130	#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
5b15fd98 HS	131	#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
	132	CONFIG_SYS_NAND_PAGE_SIZE)
	133	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	134	#define CONFIG_SYS_NAND_ECCSIZE 256
	135	#define CONFIG_SYS_NAND_ECCBYTES 3
	136	#define CONFIG_SYS_NAND_OOBSIZE 64
	137	#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
	138	48, 49, 50, 51, 52, 53, 54, 55, \
	139	56, 57, 58, 59, 60, 61, 62, 63, }
	140
	141	#define CONFIG_SPL_ATMEL_SIZE
	142	#define CONFIG_SYS_MASTER_CLOCK 132096000
	143	#define AT91_PLL_LOCK_TIMEOUT 1000000
	144	#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	145	#define CONFIG_SYS_MCKR 0x1301
	146	#define CONFIG_SYS_MCKR_CSS 0x1302
	147
b89ac72a	148	#endif