[people/ms/u-boot.git] / include / configs / cpu9260.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * (C) Copyright 2009
 * Eric Benard <eric@eukrea.com>
 *
 * Configuration settings for the Eukrea CPU9260 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* to be removed once maemory-map.h is fixed */
#define AT91_BASE_SYS	0xffffe800
#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)

#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
#define CONFIG_SYS_HZ		1000
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

#if defined(CONFIG_CPU9G20)
#define CONFIG_AT91SAM9G20
#elif defined(CONFIG_CPU9260)
#define CONFIG_AT91SAM9260
#else
#error "Unknown board"
#endif

#include <asm/arch/hardware.h>

#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#if defined(CONFIG_NANDBOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE           0x23f00000
#else
#define CONFIG_SYS_TEXT_BASE           0x00000000
#endif

/* clocks */
#if defined(CONFIG_CPU9G20)
#define MASTER_PLL_DIV		0x01
#define MASTER_PLL_MUL		0x2B
#elif defined(CONFIG_CPU9260)
#define MASTER_PLL_DIV		0x09
#define MASTER_PLL_MUL		0x61
#endif

/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_OUT |						\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#endif

#if defined(CONFIG_CPU9G20)
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_CSS_PLLA |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_6 |	\
		 AT91_PMC_PDIV_2)
#define	CONFIG_SYS_MCKR2_VAL		\
		CONFIG_SYS_MCKR1_VAL
#elif defined(CONFIG_CPU9260)
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_CSS_SLOW |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_CSS_PLLA |	\
		 AT91_PMC_PRES_1 |	\
		 AT91SAM9_PMC_MDIV_2 |	\
		 AT91_PMC_PDIV_1)
#endif

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000

/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
		(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
		AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x287
/* SDRAMC_CR - Configuration register*/
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
		(AT91_SDRAMC_NC_9 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (9 << 12) |	/* Row Cycle Delay */			\
		 (3 << 16) |	/* Row Precharge Delay */		\
		 (3 << 20) |	/* Row to Column Delay */		\
		 (6 << 24) |	/* Active to Precharge Delay */		\
		 (10 << 28))	/* Exit Self Refresh to Active Delay */

#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
		(AT91_SDRAMC_NC_10 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (9 << 12) |	/* Row Cycle Delay */			\
		 (3 << 16) |	/* Row Precharge Delay */		\
		 (3 << 20) |	/* Row to Column Delay */		\
		 (6 << 24) |	/* Active to Precharge Delay */		\
		 (10 << 28))	/* Exit Self Refresh to Active Delay */
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
		(AT91_SDRAMC_NC_9 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (7 << 12) |	/* Row Cycle Delay */			\
		 (2 << 16) |	/* Row Precharge Delay */		\
		 (2 << 20) |	/* Row to Column Delay */		\
		 (5 << 24) |	/* Active to Precharge Delay */		\
		 (8 << 28))	/* Exit Self Refresh to Active Delay */

#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
		(AT91_SDRAMC_NC_10 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_2 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |	/* Write Recovery Delay */		\
		 (7 << 12) |	/* Row Cycle Delay */			\
		 (2 << 16) |	/* Row Precharge Delay */		\
		 (2 << 20) |	/* Row to Column Delay */		\
		 (5 << 24) |	/* Active to Precharge Delay */		\
		 (8 << 28))	/* Exit Self Refresh to Active Delay */
#endif

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit */
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |	\
		 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(3))
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |	\
		 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(2))
#endif

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |			\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

/*
 * Hardware drivers
 */
#define CONFIG_AT91SAM9_WATCHDOG
#define CONFIG_AT91_GPIO
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
#define CONFIG_USART_ID		ATMEL_ID_SYS

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_128MB
#else
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_64MB
#endif

/* NAND flash */
#define CONFIG_NAND_ATMEL
#define NAND_MAX_CHIPS				1
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)

/* NOR flash */
#if defined(CONFIG_NANDBOOT)
#define CONFIG_SYS_NO_FLASH
#else
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1				0x10000000
#define PHYS_FLASH_2				0x12000000
#define CONFIG_SYS_FLASH_BANKS_LIST		\
		{ PHYS_FLASH_1, PHYS_FLASH_2 }
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		(255+4)
#define CONFIG_SYS_MAX_FLASH_BANKS		2
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
#endif

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT			20
#define CONFIG_MACB_SEARCH_PHY

/* LEDS */
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_RED				0
#define STATUS_LED_GREEN			1
#define STATUS_LED_YELLOW			2
#define STATUS_LED_BLUE				3
/* Red */
#define STATUS_LED_BIT				STATUS_LED_RED
#define STATUS_LED_STATE			STATUS_LED_OFF
#define STATUS_LED_PERIOD			(CONFIG_SYS_HZ / 2)
/* Green */
#define STATUS_LED_BIT1				STATUS_LED_GREEN
#define STATUS_LED_STATE1			STATUS_LED_OFF
#define STATUS_LED_PERIOD1			(CONFIG_SYS_HZ / 2)
/* Yellow */
#define STATUS_LED_BIT2				STATUS_LED_YELLOW
#define STATUS_LED_STATE2			STATUS_LED_OFF
#define STATUS_LED_PERIOD2			(CONFIG_SYS_HZ / 2)
/* Blue */
#define STATUS_LED_BIT3				STATUS_LED_BLUE
#define STATUS_LED_STATE3			STATUS_LED_ON
#define STATUS_LED_PERIOD3			(CONFIG_SYS_HZ / 2)
/* Optional value */
#define STATUS_LED_BOOT				STATUS_LED_BIT

#define CONFIG_RED_LED				AT91_PIO_PORTC, 11
#define CONFIG_GREEN_LED			AT91_PIO_PORTC, 12
#define CONFIG_YELLOW_LED			AT91_PIO_PORTC, 7
#define CONFIG_BLUE_LED				AT91_PIO_PORTC, 9

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g20"
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE

#define CONFIG_SYS_LOAD_ADDR			0x21000000
#define CONFIG_LOADADDR				CONFIG_SYS_LOAD_ADDR

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			\
	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)

#if defined(CONFIG_NANDBOOT)
#define CONFIG_SYS_USE_NANDFLASH
#undef CONFIG_SYS_USE_FLASH
#else
#define CONFIG_SYS_USE_FLASH
#undef CONFIG_SYS_USE_NANDFLASH
#endif

#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_BASEDIR	"cpu9G20"
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_BASEDIR	"cpu9260"
#endif

#if defined(CONFIG_SYS_USE_FLASH)
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_SECT_SIZE		0x20000
#define	CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BOOTCOMMAND		"run flashboot"

#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"256k(u-boot)ro,"	\
		"128k(u-boot-env)ro,"	\
		"1792k(kernel),"	\
		"-(rootfs);"		\
	"atmel_nand:-(nand)"

#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
		"run ramargs;bootm 22000000\0"			\
	"flashboot=run ramargs;bootm 0x10060000\0"		\
	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
	"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect "	\
		"off 0x10000000 0x1003ffff;erase 0x10000000 "	\
		"0x1003ffff;cp.b 0x24000000 0x10000000 "	\
		"$(filesize)\0" \
	"updtui=tftp 0x24000000 $(basedir)/uImage;protect off"	\
		" 0x10060000 0x1021ffff;erase 0x10060000 "	\
		"0x1021ffff;cp.b 0x24000000 0x10060000 "	\
		"$(filesize)\0" \
	"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; "	\
		"protect off 0x10220000 0x13ffffff;erase "	\
		"0x10220000 0x13ffffff;cp.b 0x24000000 "	\
		"0x10220000 $(filesize)\0" \
	""
#elif defined(CONFIG_NANDBOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SECT_SIZE		0x20000
#define	CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BOOTCOMMAND		"run flashboot"

#define MTDIDS_DEFAULT		"nand0=atmel_nand"
#define MTDPARTS_DEFAULT		\
	"mtdparts=atmel_nand:"		\
		"128k(bootstrap)ro,"	\
		"256k(u-boot)ro,"	\
		"128k(u-boot-env)ro,"	\
		"128k(u-boot-env2)ro,"	\
		"2M(kernel),"	\
		"-(rootfs)"

#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "	\
	"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" MTDIDS_DEFAULT "\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,5\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
		"run ramargs;bootm 22000000\0"			\
	"flashboot=run ramargs; nand read 0x22000000 0xA0000 "	\
		"0x200000; bootm 0x22000000\0"			\
	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
	"u-boot=u-boot-eukrea-cpu9260.bin\0"			\
	"kernel=uImage-eukrea-cpu9260.bin\0"			\
	"rootfs=image-eukrea-cpu9260.ubi\0"			\
	"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "	\
		"nand erase 20000 40000; "			\
		"nand write ${loadaddr} 20000 40000\0"		\
	"updtui=tftp ${loadaddr} $(basedir)/${kernel}; "	\
		"nand erase a0000 200000; "			\
		"nand write ${loadaddr} a0000 200000\0"		\
	"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "	\
		"nand erase  2a0000 fd60000; "			\
		"nand write ${loadaddr} 2a0000 ${filesize}\0"
#endif

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#if defined(CONFIG_CPU9G20)
#define CONFIG_SYS_PROMPT		"CPU9G20=> "
#elif defined(CONFIG_CPU9260)
#define CONFIG_SYS_PROMPT		"CPU9260=> "
#endif
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SILENT_CONSOLE
#define CONFIG_NETCONSOLE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		\
		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
				GENERATED_GBL_DATA_SIZE)

#define CONFIG_STACKSIZE		(32 * 1024)

#if defined(CONFIG_USE_IRQ)
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
23b80982 TR	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Ilko Iliev <www.ronetix.at>
	6	*
	7	* (C) Copyright 2009
	8	* Eric Benard <eric@eukrea.com>
	9	*
	10	* Configuration settings for the Eukrea CPU9260 board.
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
c2b2a07e EB	34	/* to be removed once maemory-map.h is fixed */
	35	#define AT91_BASE_SYS 0xffffe800
	36	#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
23b80982	37
7c966a8b	38	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
23b80982	39	#define CONFIG_SYS_HZ 1000
95d50e5c	40	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
23b80982 TR	41
23b80982 TR	42	#if defined(CONFIG_CPU9G20)
c2b2a07e	43	#define CONFIG_AT91SAM9G20
23b80982	44	#elif defined(CONFIG_CPU9260)
c2b2a07e	45	#define CONFIG_AT91SAM9260
23b80982 TR	46	#else
	47	#error "Unknown board"
	48	#endif
	49
95d50e5c EB	50	#include <asm/arch/hardware.h>
95d50e5c EB	51
c2b2a07e	52	#define CONFIG_AT91FAMILY
23b80982 TR	53	#define CONFIG_ARCH_CPU_INIT
23b80982 TR	54	#undef CONFIG_USE_IRQ
c2b2a07e EB	55	#define CONFIG_DISPLAY_CPUINFO
c2b2a07e EB	56	#define CONFIG_BOARD_EARLY_INIT_F
23b80982	57
c2b2a07e EB	58	#define CONFIG_CMDLINE_TAG
	59	#define CONFIG_SETUP_MEMORY_TAGS
	60	#define CONFIG_INITRD_TAG
	61
	62	#if defined(CONFIG_NANDBOOT)
	63	#define CONFIG_SKIP_LOWLEVEL_INIT
	64	#define CONFIG_SYS_TEXT_BASE 0x23f00000
	65	#else
	66	#define CONFIG_SYS_TEXT_BASE 0x00000000
	67	#endif
23b80982 TR	68
	69	/* clocks */
	70	#if defined(CONFIG_CPU9G20)
	71	#define MASTER_PLL_DIV 0x01
	72	#define MASTER_PLL_MUL 0x2B
	73	#elif defined(CONFIG_CPU9260)
	74	#define MASTER_PLL_DIV 0x09
	75	#define MASTER_PLL_MUL 0x61
	76	#endif
	77
	78	/* CKGR_MOR - enable main osc. */
	79	#define CONFIG_SYS_MOR_VAL \
	80	(AT91_PMC_MOSCEN \| \
	81	(255 << 8)) /* Main Oscillator Start-up Time */
	82	#if defined(CONFIG_CPU9G20)
	83	#define CONFIG_SYS_PLLAR_VAL \
	84	(AT91_PMC_PLLA_WR_ERRATA \| /* Bit 29 must be 1 when prog */ \
	85	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	86	#elif defined(CONFIG_CPU9260)
	87	#define CONFIG_SYS_PLLAR_VAL \
	88	(AT91_PMC_PLLA_WR_ERRATA \| /* Bit 29 must be 1 when prog */ \
	89	AT91_PMC_OUT \| \
	90	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	91	#endif
	92
	93	#if defined(CONFIG_CPU9G20)
	94	#define CONFIG_SYS_MCKR1_VAL \
	95	(AT91_PMC_CSS_PLLA \| \
	96	AT91_PMC_PRES_1 \| \
	97	AT91SAM9_PMC_MDIV_6 \| \
	98	AT91_PMC_PDIV_2)
	99	#define CONFIG_SYS_MCKR2_VAL \
	100	CONFIG_SYS_MCKR1_VAL
	101	#elif defined(CONFIG_CPU9260)
	102	#define CONFIG_SYS_MCKR1_VAL \
	103	(AT91_PMC_CSS_SLOW \| \
	104	AT91_PMC_PRES_1 \| \
	105	AT91SAM9_PMC_MDIV_2 \| \
	106	AT91_PMC_PDIV_1)
	107	#define CONFIG_SYS_MCKR2_VAL \
	108	(AT91_PMC_CSS_PLLA \| \
	109	AT91_PMC_PRES_1 \| \
	110	AT91SAM9_PMC_MDIV_2 \| \
	111	AT91_PMC_PDIV_1)
	112	#endif
	113
	114	/* define PDC[31:16] as DATA[31:16] */
	115	#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
	116	/* no pull-up for D[31:16] */
	117	#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
	118
	119	/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
	120	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
c2b2a07e EB	121	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_EBI_CS1A \| \
c2b2a07e EB	122	AT91_MATRIX_CSA_EBI_CS3A \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
23b80982 TR	123
	124	/* SDRAM */
	125	/* SDRAMC_MR Mode register */
	126	#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
	127	/* SDRAMC_TR - Refresh Timer register */
	128	#define CONFIG_SYS_SDRC_TR_VAL1 0x287
	129	/* SDRAMC_CR - Configuration register*/
	130	#if defined(CONFIG_CPU9G20)
	131	#define CONFIG_SYS_SDRC_CR_VAL_64MB \
	132	(AT91_SDRAMC_NC_9 \| \
	133	AT91_SDRAMC_NR_13 \| \
	134	AT91_SDRAMC_NB_4 \| \
	135	AT91_SDRAMC_CAS_2 \| \
	136	AT91_SDRAMC_DBW_32 \| \
	137	(2 << 8) \| /* Write Recovery Delay */ \
	138	(9 << 12) \| /* Row Cycle Delay */ \
	139	(3 << 16) \| /* Row Precharge Delay */ \
	140	(3 << 20) \| /* Row to Column Delay */ \
	141	(6 << 24) \| /* Active to Precharge Delay */ \
	142	(10 << 28)) /* Exit Self Refresh to Active Delay */
	143
	144	#define CONFIG_SYS_SDRC_CR_VAL_128MB \
	145	(AT91_SDRAMC_NC_10 \| \
	146	AT91_SDRAMC_NR_13 \| \
	147	AT91_SDRAMC_NB_4 \| \
	148	AT91_SDRAMC_CAS_2 \| \
	149	AT91_SDRAMC_DBW_32 \| \
	150	(2 << 8) \| /* Write Recovery Delay */ \
	151	(9 << 12) \| /* Row Cycle Delay */ \
	152	(3 << 16) \| /* Row Precharge Delay */ \
	153	(3 << 20) \| /* Row to Column Delay */ \
	154	(6 << 24) \| /* Active to Precharge Delay */ \
	155	(10 << 28)) /* Exit Self Refresh to Active Delay */
	156	#elif defined(CONFIG_CPU9260)
	157	#define CONFIG_SYS_SDRC_CR_VAL_64MB \
	158	(AT91_SDRAMC_NC_9 \| \
	159	AT91_SDRAMC_NR_13 \| \
	160	AT91_SDRAMC_NB_4 \| \
	161	AT91_SDRAMC_CAS_2 \| \
	162	AT91_SDRAMC_DBW_32 \| \
	163	(2 << 8) \| /* Write Recovery Delay */ \
	164	(7 << 12) \| /* Row Cycle Delay */ \
	165	(2 << 16) \| /* Row Precharge Delay */ \
	166	(2 << 20) \| /* Row to Column Delay */ \
	167	(5 << 24) \| /* Active to Precharge Delay */ \
	168	(8 << 28)) /* Exit Self Refresh to Active Delay */
	169
	170	#define CONFIG_SYS_SDRC_CR_VAL_128MB \
	171	(AT91_SDRAMC_NC_10 \| \
	172	AT91_SDRAMC_NR_13 \| \
	173	AT91_SDRAMC_NB_4 \| \
	174	AT91_SDRAMC_CAS_2 \| \
	175	AT91_SDRAMC_DBW_32 \| \
	176	(2 << 8) \| /* Write Recovery Delay */ \
	177	(7 << 12) \| /* Row Cycle Delay */ \
	178	(2 << 16) \| /* Row Precharge Delay */ \
	179	(2 << 20) \| /* Row to Column Delay */ \
	180	(5 << 24) \| /* Active to Precharge Delay */ \
	181	(8 << 28)) /* Exit Self Refresh to Active Delay */
	182	#endif
	183
	184	/* Memory Device Register -> SDRAM */
	185	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	186	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
187	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
188	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
189	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
190	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
191	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
192	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
193	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
194	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
195	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
196	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
197	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
198	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
199	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
200	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
201	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
202	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
203
204	/* setup SMC0, CS0 (NOR Flash) - 16-bit */
205	#if defined(CONFIG_CPU9G20)
206	#define CONFIG_SYS_SMC0_SETUP0_VAL \
c2b2a07e EB	207	(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \| \
c2b2a07e EB	208	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0))
23b80982	209	#define CONFIG_SYS_SMC0_PULSE0_VAL \
c2b2a07e EB	210	(AT91_SMC_PULSE_NWE(8) \| AT91_SMC_PULSE_NCS_WR(8) \| \
c2b2a07e EB	211	AT91_SMC_PULSE_NRD(14) \| AT91_SMC_PULSE_NCS_RD(14))
23b80982	212	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
c2b2a07e	213	(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(14))
23b80982	214	#define CONFIG_SYS_SMC0_MODE0_VAL \
c2b2a07e EB	215	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	216	AT91_SMC_MODE_DBW_16 \| \
	217	AT91_SMC_MODE_TDF \| \
	218	AT91_SMC_MODE_TDF_CYCLE(3))
23b80982 TR	219	#elif defined(CONFIG_CPU9260)
23b80982 TR	220	#define CONFIG_SYS_SMC0_SETUP0_VAL \
c2b2a07e EB	221	(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \| \
c2b2a07e EB	222	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0))
23b80982	223	#define CONFIG_SYS_SMC0_PULSE0_VAL \
c2b2a07e EB	224	(AT91_SMC_PULSE_NWE(6) \| AT91_SMC_PULSE_NCS_WR(6) \| \
c2b2a07e EB	225	AT91_SMC_PULSE_NRD(10) \| AT91_SMC_PULSE_NCS_RD(10))
23b80982	226	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
c2b2a07e	227	(AT91_SMC_CYCLE_NWE(6) \| AT91_SMC_CYCLE_NRD(10))
23b80982	228	#define CONFIG_SYS_SMC0_MODE0_VAL \
c2b2a07e EB	229	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	230	AT91_SMC_MODE_DBW_16 \| \
	231	AT91_SMC_MODE_TDF \| \
	232	AT91_SMC_MODE_TDF_CYCLE(2))
23b80982 TR	233	#endif
	234
	235	/* user reset enable */
	236	#define CONFIG_SYS_RSTC_RMR_VAL \
	237	(AT91_RSTC_KEY \| \
c2b2a07e EB	238	AT91_RSTC_CR_PROCRST \| \
	239	AT91_RSTC_MR_ERSTL(1) \| \
	240	AT91_RSTC_MR_ERSTL(2))
23b80982 TR	241
	242	/* Disable Watchdog */
	243	#define CONFIG_SYS_WDTC_WDMR_VAL \
c2b2a07e EB	244	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	245	AT91_WDT_MR_WDV(0xfff) \| \
	246	AT91_WDT_MR_WDDIS \| \
	247	AT91_WDT_MR_WDD(0xfff))
23b80982 TR	248
	249	/*
	250	* Hardware drivers
	251	*/
c2b2a07e EB	252	#define CONFIG_AT91SAM9_WATCHDOG
	253	#define CONFIG_AT91_GPIO
	254	#define CONFIG_ATMEL_USART
95d50e5c EB	255	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
95d50e5c EB	256	#define CONFIG_USART_ID ATMEL_ID_SYS
23b80982 TR	257
	258	#define CONFIG_BOOTDELAY 3
	259
	260	/*
	261	* BOOTP options
	262	*/
c2b2a07e EB	263	#define CONFIG_BOOTP_BOOTFILESIZE
	264	#define CONFIG_BOOTP_BOOTPATH
	265	#define CONFIG_BOOTP_GATEWAY
	266	#define CONFIG_BOOTP_HOSTNAME
23b80982 TR	267
	268	/*
	269	* Command line configuration.
	270	*/
	271	#include <config_cmd_default.h>
	272	#undef CONFIG_CMD_BDI
	273	#undef CONFIG_CMD_IMI
	274	#undef CONFIG_CMD_FPGA
	275	#undef CONFIG_CMD_LOADS
	276	#undef CONFIG_CMD_IMLS
	277
c2b2a07e EB	278	#define CONFIG_CMD_PING
	279	#define CONFIG_CMD_DHCP
	280	#define CONFIG_CMD_NAND
	281	#define CONFIG_CMD_USB
	282	#define CONFIG_CMD_FAT
	283	#define CONFIG_CMD_MII
23b80982 TR	284
	285	/* SDRAM */
	286	#define CONFIG_NR_DRAM_BANKS 1
c2b2a07e	287	#define CONFIG_SYS_SDRAM_BASE 0x20000000
23b80982	288	#if defined(CONFIG_CPU9260_128M) \|\| defined(CONFIG_CPU9G20_128M)
c2b2a07e	289	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
23b80982 TR	290	#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
23b80982 TR	291	#else
c2b2a07e	292	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
23b80982 TR	293	#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
	294	#endif
	295
	296	/* NAND flash */
c2b2a07e	297	#define CONFIG_NAND_ATMEL
23b80982 TR	298	#define NAND_MAX_CHIPS 1
	299	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	300	#define CONFIG_SYS_NAND_BASE 0x40000000
	301	#define CONFIG_SYS_NAND_DBW_8 1
c2b2a07e EB	302	#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
c2b2a07e EB	303	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
23b80982 TR	304	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	305	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	306
	307	/* NOR flash */
c2b2a07e EB	308	#if defined(CONFIG_NANDBOOT)
	309	#define CONFIG_SYS_NO_FLASH
	310	#else
	311	#define CONFIG_SYS_FLASH_CFI
	312	#define CONFIG_FLASH_CFI_DRIVER
23b80982 TR	313	#define PHYS_FLASH_1 0x10000000
	314	#define PHYS_FLASH_2 0x12000000
	315	#define CONFIG_SYS_FLASH_BANKS_LIST \
	316	{ PHYS_FLASH_1, PHYS_FLASH_2 }
	317	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	318	#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
	319	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	320	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
c2b2a07e EB	321	#define CONFIG_SYS_FLASH_EMPTY_INFO
	322	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	323	#define CONFIG_SYS_FLASH_PROTECTION
23b80982	324	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
c2b2a07e	325	#endif
23b80982 TR	326
23b80982 TR	327	/* Ethernet */
c2b2a07e EB	328	#define CONFIG_MACB
c2b2a07e EB	329	#define CONFIG_RMII
23b80982	330	#define CONFIG_NET_RETRY_COUNT 20
c2b2a07e	331	#define CONFIG_MACB_SEARCH_PHY
23b80982 TR	332
	333	/* LEDS */
	334	/* Status LED */
c2b2a07e EB	335	#define CONFIG_STATUS_LED
c2b2a07e EB	336	#define CONFIG_BOARD_SPECIFIC_LED
23b80982 TR	337	#define STATUS_LED_RED 0
	338	#define STATUS_LED_GREEN 1
	339	#define STATUS_LED_YELLOW 2
	340	#define STATUS_LED_BLUE 3
	341	/* Red */
	342	#define STATUS_LED_BIT STATUS_LED_RED
	343	#define STATUS_LED_STATE STATUS_LED_OFF
	344	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	345	/* Green */
	346	#define STATUS_LED_BIT1 STATUS_LED_GREEN
	347	#define STATUS_LED_STATE1 STATUS_LED_OFF
	348	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	349	/* Yellow */
	350	#define STATUS_LED_BIT2 STATUS_LED_YELLOW
	351	#define STATUS_LED_STATE2 STATUS_LED_OFF
	352	#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
	353	/* Blue */
	354	#define STATUS_LED_BIT3 STATUS_LED_BLUE
	355	#define STATUS_LED_STATE3 STATUS_LED_ON
	356	#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
	357	/* Optional value */
	358	#define STATUS_LED_BOOT STATUS_LED_BIT
	359
c2b2a07e EB	360	#define CONFIG_RED_LED AT91_PIO_PORTC, 11
	361	#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
	362	#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
	363	#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
23b80982 TR	364
23b80982 TR	365	/* USB */
c2b2a07e EB	366	#define CONFIG_USB_ATMEL
	367	#define CONFIG_USB_OHCI_NEW
	368	#define CONFIG_DOS_PARTITION
	369	#define CONFIG_SYS_USB_OHCI_CPU_INIT
23b80982	370	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
c2b2a07e EB	371	#if defined(CONFIG_CPU9G20)
	372	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
	373	#elif defined(CONFIG_CPU9260)
23b80982	374	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
c2b2a07e	375	#endif
23b80982	376	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
c2b2a07e	377	#define CONFIG_USB_STORAGE
23b80982 TR	378
23b80982 TR	379	#define CONFIG_SYS_LOAD_ADDR 0x21000000
c2b2a07e	380	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
23b80982	381
c2b2a07e EB	382	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	383	#define CONFIG_SYS_MEMTEST_END \
	384	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
23b80982	385
c2b2a07e EB	386	#if defined(CONFIG_NANDBOOT)
	387	#define CONFIG_SYS_USE_NANDFLASH
	388	#undef CONFIG_SYS_USE_FLASH
	389	#else
	390	#define CONFIG_SYS_USE_FLASH
23b80982	391	#undef CONFIG_SYS_USE_NANDFLASH
c2b2a07e EB	392	#endif
	393
	394	#if defined(CONFIG_CPU9G20)
	395	#define CONFIG_SYS_BASEDIR "cpu9G20"
	396	#elif defined(CONFIG_CPU9260)
	397	#define CONFIG_SYS_BASEDIR "cpu9260"
	398	#endif
23b80982 TR	399
23b80982 TR	400	#if defined(CONFIG_SYS_USE_FLASH)
c2b2a07e	401	#define CONFIG_ENV_IS_IN_FLASH
23b80982 TR	402	#define CONFIG_ENV_OFFSET 0x40000
	403	#define CONFIG_ENV_SECT_SIZE 0x20000
	404	#define CONFIG_ENV_SIZE 0x20000
c2b2a07e	405	#define CONFIG_ENV_OVERWRITE
23b80982 TR	406
	407	#define CONFIG_BOOTCOMMAND "run flashboot"
	408
c2b2a07e	409	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
23b80982 TR	410	#define MTDPARTS_DEFAULT \
	411	"mtdparts=physmap-flash.0:" \
	412	"256k(u-boot)ro," \
	413	"128k(u-boot-env)ro," \
	414	"1792k(kernel)," \
	415	"-(rootfs);" \
	416	"atmel_nand:-(nand)"
	417
	418	#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
	419
23b80982 TR	420	#define CONFIG_EXTRA_ENV_SETTINGS \
	421	"mtdids=" MTDIDS_DEFAULT "\0" \
	422	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	423	"partition=nand0,0\0" \
	424	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
c2b2a07e	425	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
23b80982 TR	426	"run ramargs;bootm 22000000\0" \
	427	"flashboot=run ramargs;bootm 0x10060000\0" \
	428	"basedir=" CONFIG_SYS_BASEDIR "\0" \
	429	"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
	430	"off 0x10000000 0x1003ffff;erase 0x10000000 " \
	431	"0x1003ffff;cp.b 0x24000000 0x10000000 " \
	432	"$(filesize)\0" \
	433	"updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
	434	" 0x10060000 0x1021ffff;erase 0x10060000 " \
	435	"0x1021ffff;cp.b 0x24000000 0x10060000 " \
	436	"$(filesize)\0" \
	437	"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
	438	"protect off 0x10220000 0x13ffffff;erase " \
	439	"0x10220000 0x13ffffff;cp.b 0x24000000 " \
	440	"0x10220000 $(filesize)\0" \
	441	""
c2b2a07e EB	442	#elif defined(CONFIG_NANDBOOT)
	443	#define CONFIG_ENV_IS_IN_NAND
	444	#define CONFIG_ENV_OFFSET 0x60000
	445	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	446	#define CONFIG_ENV_SECT_SIZE 0x20000
	447	#define CONFIG_ENV_SIZE 0x20000
	448	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	449	#define CONFIG_ENV_OVERWRITE
	450
	451	#define CONFIG_BOOTCOMMAND "run flashboot"
	452
	453	#define MTDIDS_DEFAULT "nand0=atmel_nand"
	454	#define MTDPARTS_DEFAULT \
	455	"mtdparts=atmel_nand:" \
	456	"128k(bootstrap)ro," \
	457	"256k(u-boot)ro," \
	458	"128k(u-boot-env)ro," \
	459	"128k(u-boot-env2)ro," \
	460	"2M(kernel)," \
	461	"-(rootfs)"
	462
	463	#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
	464	"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
	465
	466	#define CONFIG_EXTRA_ENV_SETTINGS \
	467	"mtdids=" MTDIDS_DEFAULT "\0" \
	468	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	469	"partition=nand0,5\0" \
	470	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	471	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
	472	"run ramargs;bootm 22000000\0" \
	473	"flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
	474	"0x200000; bootm 0x22000000\0" \
	475	"basedir=" CONFIG_SYS_BASEDIR "\0" \
	476	"u-boot=u-boot-eukrea-cpu9260.bin\0" \
	477	"kernel=uImage-eukrea-cpu9260.bin\0" \
	478	"rootfs=image-eukrea-cpu9260.ubi\0" \
	479	"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
	480	"nand erase 20000 40000; " \
	481	"nand write ${loadaddr} 20000 40000\0" \
	482	"updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
	483	"nand erase a0000 200000; " \
	484	"nand write ${loadaddr} a0000 200000\0" \
	485	"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
	486	"nand erase 2a0000 fd60000; " \
	487	"nand write ${loadaddr} 2a0000 ${filesize}\0"
23b80982 TR	488	#endif
	489
	490	#define CONFIG_BAUDRATE 115200
	491	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
	492
	493	#if defined(CONFIG_CPU9G20)
	494	#define CONFIG_SYS_PROMPT "CPU9G20=> "
	495	#elif defined(CONFIG_CPU9260)
	496	#define CONFIG_SYS_PROMPT "CPU9260=> "
	497	#endif
	498	#define CONFIG_SYS_CBSIZE 256
	499	#define CONFIG_SYS_MAXARGS 16
	500	#define CONFIG_SYS_PBSIZE \
	501	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
c2b2a07e EB	502	#define CONFIG_SYS_LONGHELP
	503	#define CONFIG_CMDLINE_EDITING
	504	#define CONFIG_SILENT_CONSOLE
	505	#define CONFIG_NETCONSOLE
23b80982 TR	506
	507	/*
	508	* Size of malloc() pool
	509	*/
	510	#define CONFIG_SYS_MALLOC_LEN \
	511	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
23b80982	512
c2b2a07e EB	513	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
	514	GENERATED_GBL_DATA_SIZE)
	515
23b80982 TR	516	#define CONFIG_STACKSIZE (32 * 1024)
	517
	518	#if defined(CONFIG_USE_IRQ)
	519	#error CONFIG_USE_IRQ not supported
	520	#endif
	521
	522	#endif