[people/ms/u-boot.git] / include / configs / cradle.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
#define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */

#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x10000300
#define CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT

/*
 * select serial console configuration
 */
#define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE         115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define CONFIG_BOOTDELAY        3
#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
#define CONFIG_NETMASK          255.255.0.0
#define CONFIG_IPADDR           192.168.0.21
#define CONFIG_SERVERIP         192.168.0.250
#define CONFIG_BOOTCOMMAND      "bootm 40000"
#define CONFIG_CMDLINE_TAG

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP                            /* undef to save memory         */
#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS             16              /* max number of command args   */
#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */

#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR           0xa2000000      /* default load address */

#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */

						/* valid baudrates */
#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
#define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
#define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
#define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */

#define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */

#define CFG_DRAM_BASE           0xa0000000
#define CFG_DRAM_SIZE           0x04000000

#define CFG_FLASH_BASE          PHYS_FLASH_1

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS     1     /* max number of memory banks           */
#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR				0x00020000	/* absolute address for now   */
#define CFG_ENV_SIZE				0x20000	   /* 8K ouch, this may later be */

/******************************************************************************
 *
 * CPU specific defines
 *
 ******************************************************************************/

/*
 * GPIO settings
 *
 * GPIO pin assignments
 * GPIO     Name        Dir Out AF
 * 0        NC
 * 1        NC
 * 2        SIRQ1       I
 * 3        SIRQ2       I
 * 4        SIRQ3       I
 * 5        DMAACK1     O   0
 * 6        DMAACK2     O   0
 * 7        DMAACK3     O   0
 * 8        TC1         O   0
 * 9        TC2         O   0
 * 10       TC3         O   0
 * 11       nDMAEN      O   1
 * 12       AENCTRL     O   0
 * 13       PLDTC       O   0
 * 14       ETHIRQ      I
 * 15       NC
 * 16       NC
 * 17       NC
 * 18       RDY         I
 * 19       DMASIO      I
 * 20       ETHIRQ      NC
 * 21       NC
 * 22       PGMEN       O   1    FIXME for debug only enable flash
 * 23       NC
 * 24       NC
 * 25       NC
 * 26       NC
 * 27       NC
 * 28       NC
 * 29       NC
 * 30       NC
 * 31       NC
 * 32       NC
 * 33       NC
 * 34       FFRXD       I       01
 * 35       FFCTS       I       01
 * 36       FFDCD       I       01
 * 37       FFDSR       I       01
 * 38       FFRI        I       01
 * 39       FFTXD       O   1   10
 * 40       FFDTR       O   0   10
 * 41       FFRTS       O   0   10
 * 42       RS232FOFF   O   0   00
 * 43       NC
 * 44       NC
 * 45       IRSL0       O   0
 * 46       IRRX0       I       01
 * 47       IRTX0       O   0   10
 * 48       NC
 * 49       nIOWE       O   0
 * 50       NC
 * 51       NC
 * 52       NC
 * 53       NC
 * 54       NC
 * 55       NC
 * 56       NC
 * 57       NC
 * 58       DKDIRQ      I
 * 59       NC
 * 60       NC
 * 61       NC
 * 62       NC
 * 63       NC
 * 64       COMLED      O   0
 * 65       COMLED      O   0
 * 66       COMLED      O   0
 * 67       COMLED      O   0
 * 68       COMLED      O   0
 * 69       COMLED      O   0
 * 70       COMLED      O   0
 * 71       COMLED      O   0
 * 72       NC
 * 73       NC
 * 74       NC
 * 75       NC
 * 76       NC
 * 77       NC
 * 78       CSIO        O   1
 * 79       NC
 * 80       CSETH       O   1
 *
 * NOTE: All NC's are defined to be outputs
 *
 */
/* Pin direction control */
/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
#define CFG_GPDR0_VAL       0xfff3bf02
#define CFG_GPDR1_VAL       0xfbffbf83
#define CFG_GPDR2_VAL       0x0001ffff
/* Set and Clear registers */
#define CFG_GPSR0_VAL       0x00400800
#define CFG_GPSR1_VAL       0x00000480
#define CFG_GPSR2_VAL       0x00014000
#define CFG_GPCR0_VAL       0x00000000
#define CFG_GPCR1_VAL       0x00000000
#define CFG_GPCR2_VAL       0x00000000
/* Edge detect registers (these are set by the kernel) */
#define CFG_GRER0_VAL       0x00000000
#define CFG_GRER1_VAL       0x00000000
#define CFG_GRER2_VAL       0x00000000
#define CFG_GFER0_VAL       0x00000000
#define CFG_GFER1_VAL       0x00000000
#define CFG_GFER2_VAL       0x00000000
/* Alternate function registers */
#define CFG_GAFR0_L_VAL     0x00000000
#define CFG_GAFR0_U_VAL     0x00000010
#define CFG_GAFR1_L_VAL     0x900a9550
#define CFG_GAFR1_U_VAL     0x00000008
#define CFG_GAFR2_L_VAL     0x20000000
#define CFG_GAFR2_U_VAL     0x00000002

/*
 * Clocks, power control and interrupts
 */
#define CFG_PSSR_VAL        0x00000020
#define CFG_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
#define CFG_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
#define CFG_ICMR_VAL        0x00000000  /* No interrupts enabled        */

/* FIXME
 *
 * RTC settings
 * Watchdog
 *
 */

/*
 * Memory settings
 *
 * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
 *       Verify timings on all
 */
#define CFG_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
/*#define CFG_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
#define CFG_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
#define CFG_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
#ifdef REDBOOT_WAY
#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
#define CFG_MDMRS_VAL       0x00000000
#define CFG_MDREFR_VAL      0x00018018
#else
#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
#define CFG_MDMRS_VAL       0x00000000
#define CFG_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
#endif

/*
 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
 */
#define CFG_MECR_VAL          0x00000000
#define CFG_MCMEM0_VAL        0x00010504
#define CFG_MCMEM1_VAL        0x00010504
#define CFG_MCATT0_VAL        0x00010504
#define CFG_MCATT1_VAL        0x00010504
#define CFG_MCIO0_VAL         0x00004715
#define CFG_MCIO1_VAL         0x00004715

/* Board specific defines */

/* LED defines */
#define YELLOW    0x03
#define RED       0x02
#define GREEN     0x01
#define OFF       0x00
#define LED_IRDA0 0
#define LED_IRDA1 2
#define LED_IRDA2 4
#define LED_IRDA3 6
#define CRADLE_LED_SET_REG GPSR2
#define CRADLE_LED_CLR_REG GPCR2

/* SuperIO defines */
#define CRADLE_SIO_INDEX      0x2e
#define CRADLE_SIO_DATA       0x2f

/* IO defines */
#define CRADLE_CPLD_PHYS      0x08000000
#define CRADLE_SIO1_PHYS      0x08100000
#define CRADLE_SIO2_PHYS      0x08200000
#define CRADLE_SIO3_PHYS      0x08300000
#define CRADLE_ETH_PHYS       0x10000000

#ifndef __ASSEMBLY__

/* global prototypes */
void led_code(int code, int color);

#endif

#endif  /* __CONFIG_H */
Commit	Line	Data
d9fd6ff5 WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
d9fd6ff5 WD	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	36	#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
	37
	38	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	39
	40	/*
	41	* Size of malloc() pool
	42	*/
699b13a6	43	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
a8c7c708	44	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
d9fd6ff5 WD	45
	46	/*
	47	* Hardware drivers
	48	*/
	49	#define CONFIG_DRIVER_SMC91111
	50	#define CONFIG_SMC91111_BASE 0x10000300
	51	#define CONFIG_SMC91111_EXT_PHY
	52	#define CONFIG_SMC_USE_32_BIT
	53
	54	/*
	55	* select serial console configuration
	56	*/
	57	#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
	58
	59	/* allow to overwrite serial and ethaddr */
	60	#define CONFIG_ENV_OVERWRITE
	61
	62	#define CONFIG_BAUDRATE 115200
	63
d9fd6ff5	64
80ff4f99 JL	65	/*
	66	* BOOTP options
	67	*/
	68	#define CONFIG_BOOTP_BOOTFILESIZE
	69	#define CONFIG_BOOTP_BOOTPATH
	70	#define CONFIG_BOOTP_GATEWAY
	71	#define CONFIG_BOOTP_HOSTNAME
	72
	73
37e4f24b JL	74	/*
	75	* Command line configuration.
	76	*/
	77	#include <config_cmd_default.h>
	78
d9fd6ff5 WD	79
	80	#define CONFIG_BOOTDELAY 3
	81	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
	82	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	83	#define CONFIG_NETMASK 255.255.0.0
	84	#define CONFIG_IPADDR 192.168.0.21
	85	#define CONFIG_SERVERIP 192.168.0.250
	86	#define CONFIG_BOOTCOMMAND "bootm 40000"
	87	#define CONFIG_CMDLINE_TAG
	88
	89	/*
	90	* Miscellaneous configurable options
	91	*/
	92	#define CFG_LONGHELP /* undef to save memory */
	93	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	94	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	95	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	96	#define CFG_MAXARGS 16 /* max number of command args */
	97	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	98
	99	#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
	100	#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	101
	102	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	103
	104	#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
	105
	106	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	107	#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
	108
8bde7f77	109	/* valid baudrates */
d9fd6ff5 WD	110	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	111
	112	/*
	113	* Stack sizes
	114	*
	115	* The stack sizes are set up in start.S using the settings below
	116	*/
	117	#define CONFIG_STACKSIZE (1281024) / regular stack */
	118	#ifdef CONFIG_USE_IRQ
	119	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	120	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	121	#endif
	122
	123	/*
	124	* Physical Memory Map
	125	*/
	126	#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
	127	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	128	#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
	129	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	130	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	131	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	132	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	133	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	134	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	135
	136	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	137	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
	138	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	139
	140	#define CFG_DRAM_BASE 0xa0000000
	141	#define CFG_DRAM_SIZE 0x04000000
	142
	143	#define CFG_FLASH_BASE PHYS_FLASH_1
	144
	145	/*
	146	* FLASH and environment organization
	147	*/
	148	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	149	#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
	150
	151	/* timeout values are in ticks */
	152	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
	153	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
	154
5a1aceb0	155	#define CONFIG_ENV_IS_IN_FLASH 1
d9fd6ff5 WD	156	#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
	157	#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
	158
	159	/******************************************************************************
	160	*
	161	* CPU specific defines
	162	*
	163	******************************************************************************/
	164
	165	/*
	166	* GPIO settings
	167	*
	168	* GPIO pin assignments
	169	* GPIO Name Dir Out AF
	170	* 0 NC
	171	* 1 NC
	172	* 2 SIRQ1 I
	173	* 3 SIRQ2 I
	174	* 4 SIRQ3 I
	175	* 5 DMAACK1 O 0
	176	* 6 DMAACK2 O 0
	177	* 7 DMAACK3 O 0
	178	* 8 TC1 O 0
	179	* 9 TC2 O 0
	180	* 10 TC3 O 0
	181	* 11 nDMAEN O 1
	182	* 12 AENCTRL O 0
	183	* 13 PLDTC O 0
	184	* 14 ETHIRQ I
	185	* 15 NC
	186	* 16 NC
	187	* 17 NC
	188	* 18 RDY I
	189	* 19 DMASIO I
	190	* 20 ETHIRQ NC
	191	* 21 NC
	192	* 22 PGMEN O 1 FIXME for debug only enable flash
	193	* 23 NC
	194	* 24 NC
	195	* 25 NC
	196	* 26 NC
	197	* 27 NC
	198	* 28 NC
	199	* 29 NC
	200	* 30 NC
	201	* 31 NC
	202	* 32 NC
	203	* 33 NC
	204	* 34 FFRXD I 01
	205	* 35 FFCTS I 01
	206	* 36 FFDCD I 01
	207	* 37 FFDSR I 01
	208	* 38 FFRI I 01
	209	* 39 FFTXD O 1 10
	210	* 40 FFDTR O 0 10
	211	* 41 FFRTS O 0 10
	212	* 42 RS232FOFF O 0 00
	213	* 43 NC
	214	* 44 NC
	215	* 45 IRSL0 O 0
	216	* 46 IRRX0 I 01
	217	* 47 IRTX0 O 0 10
	218	* 48 NC
	219	* 49 nIOWE O 0
220	* 50 NC
221	* 51 NC
222	* 52 NC
223	* 53 NC
224	* 54 NC
225	* 55 NC
226	* 56 NC
227	* 57 NC
228	* 58 DKDIRQ I
229	* 59 NC
230	* 60 NC
231	* 61 NC
232	* 62 NC
233	* 63 NC
234	* 64 COMLED O 0
235	* 65 COMLED O 0
236	* 66 COMLED O 0
237	* 67 COMLED O 0
238	* 68 COMLED O 0
239	* 69 COMLED O 0
240	* 70 COMLED O 0
241	* 71 COMLED O 0
242	* 72 NC
243	* 73 NC
244	* 74 NC
245	* 75 NC
246	* 76 NC
247	* 77 NC
248	* 78 CSIO O 1
249	* 79 NC
250	* 80 CSETH O 1
251	*
252	* NOTE: All NC's are defined to be outputs
253	*
254	*/
255	/* Pin direction control */
256	/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
257	#define CFG_GPDR0_VAL 0xfff3bf02
258	#define CFG_GPDR1_VAL 0xfbffbf83
259	#define CFG_GPDR2_VAL 0x0001ffff
260	/* Set and Clear registers */
261	#define CFG_GPSR0_VAL 0x00400800
262	#define CFG_GPSR1_VAL 0x00000480
263	#define CFG_GPSR2_VAL 0x00014000
264	#define CFG_GPCR0_VAL 0x00000000
265	#define CFG_GPCR1_VAL 0x00000000
266	#define CFG_GPCR2_VAL 0x00000000
267	/* Edge detect registers (these are set by the kernel) */
268	#define CFG_GRER0_VAL 0x00000000
269	#define CFG_GRER1_VAL 0x00000000
270	#define CFG_GRER2_VAL 0x00000000
271	#define CFG_GFER0_VAL 0x00000000
272	#define CFG_GFER1_VAL 0x00000000
273	#define CFG_GFER2_VAL 0x00000000
274	/* Alternate function registers */
275	#define CFG_GAFR0_L_VAL 0x00000000
276	#define CFG_GAFR0_U_VAL 0x00000010
277	#define CFG_GAFR1_L_VAL 0x900a9550
278	#define CFG_GAFR1_U_VAL 0x00000008
279	#define CFG_GAFR2_L_VAL 0x20000000
280	#define CFG_GAFR2_U_VAL 0x00000002
281
282	/*
283	* Clocks, power control and interrupts
284	*/
285	#define CFG_PSSR_VAL 0x00000020
286	#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
287	#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
288	#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
289
290	/* FIXME
291	*
292	* RTC settings
293	* Watchdog
294	*
295	*/
296
297	/*
298	* Memory settings
299	*
300	* FIXME Can ethernet be burst read and/or write?? This is set for lubbock
301	* Verify timings on all
302	*/
303	#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
304	/#define CFG_MSC1_VAL 0x00003549 / SuperIO bank (cs2) */
305	#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
306	#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
307	#ifdef REDBOOT_WAY
308	#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
309	#define CFG_MDMRS_VAL 0x00000000
310	#define CFG_MDREFR_VAL 0x00018018
311	#else
312	#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
313	#define CFG_MDMRS_VAL 0x00000000
400558b5	314	#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
d9fd6ff5 WD	315	#endif
	316
	317	/*
	318	* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
	319	*/
	320	#define CFG_MECR_VAL 0x00000000
	321	#define CFG_MCMEM0_VAL 0x00010504
	322	#define CFG_MCMEM1_VAL 0x00010504
	323	#define CFG_MCATT0_VAL 0x00010504
	324	#define CFG_MCATT1_VAL 0x00010504
	325	#define CFG_MCIO0_VAL 0x00004715
	326	#define CFG_MCIO1_VAL 0x00004715
	327
	328	/* Board specific defines */
	329
	330	/* LED defines */
	331	#define YELLOW 0x03
	332	#define RED 0x02
	333	#define GREEN 0x01
	334	#define OFF 0x00
	335	#define LED_IRDA0 0
	336	#define LED_IRDA1 2
	337	#define LED_IRDA2 4
	338	#define LED_IRDA3 6
	339	#define CRADLE_LED_SET_REG GPSR2
	340	#define CRADLE_LED_CLR_REG GPCR2
	341
	342	/* SuperIO defines */
	343	#define CRADLE_SIO_INDEX 0x2e
	344	#define CRADLE_SIO_DATA 0x2f
	345
	346	/* IO defines */
	347	#define CRADLE_CPLD_PHYS 0x08000000
	348	#define CRADLE_SIO1_PHYS 0x08100000
	349	#define CRADLE_SIO2_PHYS 0x08200000
	350	#define CRADLE_SIO3_PHYS 0x08300000
	351	#define CRADLE_ETH_PHYS 0x10000000
	352
	353	#ifndef __ASSEMBLY__
	354
	355	/* global prototypes */
	356	void led_code(int code, int color);
	357
	358	#endif
	359
	360	#endif /* __CONFIG_H */