[people/ms/u-boot.git] / include / configs / csb272.h

/*
 * (C) Copyright 2004
 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * OS Bootstrap configuration
 *
 */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
#else
#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
#endif

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */

#if 1
#undef  CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
	"setenv bootargs console=ttyS0,38400 debug " \
	"root=/dev/ram rw ramdisk_size=4096 " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm fe000000 fe100000"
#endif

#if 0
#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
	"bootp; " \
	"setenv bootargs console=ttyS0,38400 debug " \
	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm"
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS2


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PCI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP


/*
 * Serial download configuration
 *
 */
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

/*
 * KGDB Configuration
 *
 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Miscellaneous configurable options
 *
 */
#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */

#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * watchdog configuration
 *
 */
#undef  CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * UART configuration
 *
 */
#define CONFIG_CONS_INDEX		1	/* Use UART0		*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_SYS_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
#undef  CONFIG_SYS_BASE_BAUD
#define CONFIG_BAUDRATE		38400	/* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE      \
    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * I2C configuration
 *
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* I2C slave address */

/*
 * MII PHY configuration
 *
 */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
					/* 32usec min. for LXT971A	*/
#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/

/*
 * RTC configuration
 *
 * Note that DS1307 RTC is limited to 100Khz I2C bus.
 *
 */
#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/

/*
 * PCI stuff
 *
 */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
#define PCI_HOST_FORCE		1	/* configure as pci host        */
#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */

#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */
#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*
 * IDE stuff
 *
 */
#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */

/*
 * Environment configuration
 *
 */
#define CONFIG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_EEPROM

/*
 * General Memory organization
 *
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */

#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_RAMSTART
#endif

#if defined(CONFIG_ENV_IS_IN_FLASH)
#define CONFIG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
#define CONFIG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
#define	CONFIG_ENV_SIZE		0x00001000 /* Size of Environment */
#define CONFIG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
#endif

/*
 * FLASH Device configuration
 *
 */
#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

/*
 * On Chip Memory location/size
 *
 */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

/*
 * Global info and initial stack
 *
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Miscellaneous board specific definitions
 *
 */
#define CONFIG_SYS_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */

#endif	/* __CONFIG_H */
Commit	Line	Data
cd0a9de6 WD	1	/*
	2	* (C) Copyright 2004
	3	* Tolunay Orkun, Nextio Inc., torkun@nextio.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
cd0a9de6 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
53677ef1	20	#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
cd0a9de6	21	#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
4d13cbad	22	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
cd0a9de6 WD	23	#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
	24	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	27
cd0a9de6 WD	28	/*
	29	* OS Bootstrap configuration
	30	*
	31	*/
	32
	33	#if 0
	34	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	35	#else
	36	#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
	37	#endif
	38
	39	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
	40
	41	#if 1
	42	#undef CONFIG_BOOTARGS
	43	#define CONFIG_BOOTCOMMAND \
	44	"setenv bootargs console=ttyS0,38400 debug " \
	45	"root=/dev/ram rw ramdisk_size=4096 " \
fe126d8b	46	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
cd0a9de6 WD	47	"bootm fe000000 fe100000"
	48	#endif
	49
	50	#if 0
	51	#undef CONFIG_BOOTARGS
	52	#define CONFIG_BOOTCOMMAND \
	53	"bootp; " \
	54	"setenv bootargs console=ttyS0,38400 debug " \
fe126d8b WD	55	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	56	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
cd0a9de6 WD	57	"bootm"
	58	#endif
	59
	60	/*
2fd90ce5	61	* BOOTP options
cd0a9de6	62	*/
2fd90ce5 JL	63	#define CONFIG_BOOTP_SUBNETMASK
	64	#define CONFIG_BOOTP_GATEWAY
	65	#define CONFIG_BOOTP_HOSTNAME
	66	#define CONFIG_BOOTP_BOOTPATH
	67	#define CONFIG_BOOTP_BOOTFILESIZE
	68	#define CONFIG_BOOTP_DNS2
37e4f24b JL	69
37e4f24b JL	70
cd0a9de6	71	/*
37e4f24b	72	* Command line configuration.
cd0a9de6	73	*/
37e4f24b JL	74	#include <config_cmd_default.h>
	75
	76	#define CONFIG_CMD_ASKENV
	77	#define CONFIG_CMD_BEDBUG
	78	#define CONFIG_CMD_ELF
	79	#define CONFIG_CMD_IRQ
	80	#define CONFIG_CMD_I2C
	81	#define CONFIG_CMD_PCI
	82	#define CONFIG_CMD_DATE
	83	#define CONFIG_CMD_MII
	84	#define CONFIG_CMD_PING
	85	#define CONFIG_CMD_DHCP
	86
cd0a9de6 WD	87
	88	/*
	89	* Serial download configuration
	90	*
	91	*/
	92	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	93	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
cd0a9de6 WD	94
	95	/*
	96	* KGDB Configuration
	97	*
	98	*/
37e4f24b	99	#if defined(CONFIG_CMD_KGDB)
cd0a9de6	100	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
cd0a9de6 WD	101	#endif
	102
	103	/*
	104	* Miscellaneous configurable options
	105	*
	106	*/
6d0f6bcf	107	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
cd0a9de6	108
6d0f6bcf	109	#define CONFIG_SYS_LONGHELP /* undef to save memory */
37e4f24b	110	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	111	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
cd0a9de6	112	#else
6d0f6bcf	113	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
cd0a9de6	114	#endif
6d0f6bcf JCPV	115	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	116	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	117	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
cd0a9de6	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	120	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
6d0f6bcf JCPV	121	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
6d0f6bcf JCPV	122	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
cd0a9de6 WD	123
	124	/*
	125	* For booting Linux, the board info and command line data
	126	* have to be in the first 8 MB of memory, since this is
	127	* the maximum mapped by the Linux kernel during initialization.
	128	*/
6d0f6bcf	129	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
cd0a9de6 WD	130
	131	/*
	132	* watchdog configuration
	133	*
	134	*/
	135	#undef CONFIG_WATCHDOG /* watchdog disabled */
	136
	137	/*
	138	* UART configuration
	139	*
	140	*/
550650dd SR	141	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	142	#define CONFIG_SYS_NS16550
	143	#define CONFIG_SYS_NS16550_SERIAL
	144	#define CONFIG_SYS_NS16550_REG_SIZE 1
	145	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	146
6d0f6bcf	147	#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
6d0f6bcf	148	#undef CONFIG_SYS_BASE_BAUD
cd0a9de6	149	#define CONFIG_BAUDRATE 38400 /* Default baud rate */
6d0f6bcf	150	#define CONFIG_SYS_BAUDRATE_TABLE \
cd0a9de6 WD	151	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
	152
	153	/*
	154	* I2C configuration
	155	*
	156	*/
880540de DE	157	#define CONFIG_SYS_I2C
	158	#define CONFIG_SYS_I2C_PPC4XX
	159	#define CONFIG_SYS_I2C_PPC4XX_CH0
	160	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	161	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */
cd0a9de6 WD	162
	163	/*
	164	* MII PHY configuration
	165	*
	166	*/
96e21f86	167	#define CONFIG_PPC4xx_EMAC
cd0a9de6 WD	168	#define CONFIG_MII 1 /* MII PHY management */
cd0a9de6 WD	169	#define CONFIG_PHY_ADDR 0 /* PHY address */
53677ef1	170	#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
cd0a9de6 WD	171	/* 32usec min. for LXT971A */
	172	#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
	173
	174	/*
	175	* RTC configuration
	176	*
	177	* Note that DS1307 RTC is limited to 100Khz I2C bus.
	178	*
	179	*/
	180	#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
	181
	182	/*
	183	* PCI stuff
	184	*
	185	*/
	186	#define CONFIG_PCI /* include pci support */
842033e6	187	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
cd0a9de6 WD	188	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	189	#define PCI_HOST_FORCE 1 /* configure as pci host */
	190	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	191
	192	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	193	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	194	/* resource configuration */
	195	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	196	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	199	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	200	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	201	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	202	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	203	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	204	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	205	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
cd0a9de6 WD	206
	207	/*
	208	* IDE stuff
	209	*
	210	*/
	211	#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
	212	#undef CONFIG_IDE_LED /* no led for ide supported */
	213	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	214
	215	/*
	216	* Environment configuration
	217	*
	218	*/
5a1aceb0	219	#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
9314cee6	220	#undef CONFIG_ENV_IS_IN_NVRAM
bb1f8b4f	221	#undef CONFIG_ENV_IS_IN_EEPROM
cd0a9de6 WD	222
	223	/*
	224	* General Memory organization
	225	*
	226	* Start addresses for the final memory configuration
	227	* (Set up by the startup code)
6d0f6bcf	228	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
cd0a9de6	229	*/
6d0f6bcf JCPV	230	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	231	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	232	#define CONFIG_SYS_FLASH_SIZE 0x02000000
14d0a02a	233	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	234	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
	235	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
	236
	237	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
	238	#define CONFIG_SYS_RAMSTART
cd0a9de6 WD	239	#endif
cd0a9de6 WD	240
5a1aceb0	241	#if defined(CONFIG_ENV_IS_IN_FLASH)
0e8d1586 JCPV	242	#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
	243	#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
	244	#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
	245	#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
cd0a9de6 WD	246	#endif
	247
	248	/*
	249	* FLASH Device configuration
	250	*
	251	*/
6d0f6bcf	252	#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
00b1883a	253	#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
6d0f6bcf JCPV	254	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	255	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
	256	#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
	257	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
	258	#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
	259	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
cd0a9de6 WD	260
	261	/*
	262	* On Chip Memory location/size
	263	*
	264	*/
6d0f6bcf JCPV	265	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
6d0f6bcf JCPV	266	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
cd0a9de6 WD	267
	268	/*
	269	* Global info and initial stack
	270	*
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
553f0982	273	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
25ddd1fb	274	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	275	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
cd0a9de6	276
cd0a9de6 WD	277	/*
	278	* Miscellaneous board specific definitions
	279	*
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
eeb1b77b	282	#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
cd0a9de6	283
cd0a9de6	284	#endif /* __CONFIG_H */