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cd0a9de6 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Tolunay Orkun, Nextio Inc., torkun@nextio.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
cd0a9de6 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
53677ef1 | 20 | #define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
cd0a9de6 WD |
21 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
22 | #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ | |
4d13cbad | 23 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ |
cd0a9de6 WD |
24 | #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ |
25 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
26 | ||
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
28 | ||
cd0a9de6 WD |
29 | /* |
30 | * OS Bootstrap configuration | |
31 | * | |
32 | */ | |
33 | ||
34 | #if 0 | |
35 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
36 | #else | |
37 | #define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ | |
38 | #endif | |
39 | ||
40 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ | |
41 | ||
42 | #if 1 | |
43 | #undef CONFIG_BOOTARGS | |
44 | #define CONFIG_BOOTCOMMAND \ | |
45 | "setenv bootargs console=ttyS0,38400 debug " \ | |
46 | "root=/dev/ram rw ramdisk_size=4096 " \ | |
fe126d8b | 47 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ |
cd0a9de6 WD |
48 | "bootm fe000000 fe100000" |
49 | #endif | |
50 | ||
51 | #if 0 | |
52 | #undef CONFIG_BOOTARGS | |
53 | #define CONFIG_BOOTCOMMAND \ | |
54 | "bootp; " \ | |
55 | "setenv bootargs console=ttyS0,38400 debug " \ | |
fe126d8b WD |
56 | "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
57 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
cd0a9de6 WD |
58 | "bootm" |
59 | #endif | |
60 | ||
61 | /* | |
2fd90ce5 | 62 | * BOOTP options |
cd0a9de6 | 63 | */ |
2fd90ce5 JL |
64 | #define CONFIG_BOOTP_SUBNETMASK |
65 | #define CONFIG_BOOTP_GATEWAY | |
66 | #define CONFIG_BOOTP_HOSTNAME | |
67 | #define CONFIG_BOOTP_BOOTPATH | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
69 | #define CONFIG_BOOTP_DNS2 | |
37e4f24b JL |
70 | |
71 | ||
cd0a9de6 | 72 | /* |
37e4f24b | 73 | * Command line configuration. |
cd0a9de6 | 74 | */ |
37e4f24b JL |
75 | #include <config_cmd_default.h> |
76 | ||
77 | #define CONFIG_CMD_ASKENV | |
78 | #define CONFIG_CMD_BEDBUG | |
79 | #define CONFIG_CMD_ELF | |
80 | #define CONFIG_CMD_IRQ | |
81 | #define CONFIG_CMD_I2C | |
82 | #define CONFIG_CMD_PCI | |
83 | #define CONFIG_CMD_DATE | |
84 | #define CONFIG_CMD_MII | |
85 | #define CONFIG_CMD_PING | |
86 | #define CONFIG_CMD_DHCP | |
87 | ||
cd0a9de6 WD |
88 | |
89 | /* | |
90 | * Serial download configuration | |
91 | * | |
92 | */ | |
93 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 94 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
cd0a9de6 WD |
95 | |
96 | /* | |
97 | * KGDB Configuration | |
98 | * | |
99 | */ | |
37e4f24b | 100 | #if defined(CONFIG_CMD_KGDB) |
cd0a9de6 WD |
101 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
102 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
103 | #endif | |
104 | ||
105 | /* | |
106 | * Miscellaneous configurable options | |
107 | * | |
108 | */ | |
6d0f6bcf | 109 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
cd0a9de6 | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
112 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
37e4f24b | 113 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 114 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
cd0a9de6 | 115 | #else |
6d0f6bcf | 116 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
cd0a9de6 | 117 | #endif |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
119 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
120 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
cd0a9de6 | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
123 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
cd0a9de6 | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ |
127 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
cd0a9de6 WD |
128 | |
129 | /* | |
130 | * For booting Linux, the board info and command line data | |
131 | * have to be in the first 8 MB of memory, since this is | |
132 | * the maximum mapped by the Linux kernel during initialization. | |
133 | */ | |
6d0f6bcf | 134 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
cd0a9de6 WD |
135 | |
136 | /* | |
137 | * watchdog configuration | |
138 | * | |
139 | */ | |
140 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
141 | ||
142 | /* | |
143 | * UART configuration | |
144 | * | |
145 | */ | |
550650dd SR |
146 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
147 | #define CONFIG_SYS_NS16550 | |
148 | #define CONFIG_SYS_NS16550_SERIAL | |
149 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
150 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
151 | ||
6d0f6bcf | 152 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ |
6d0f6bcf | 153 | #undef CONFIG_SYS_BASE_BAUD |
cd0a9de6 | 154 | #define CONFIG_BAUDRATE 38400 /* Default baud rate */ |
6d0f6bcf | 155 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
cd0a9de6 WD |
156 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } |
157 | ||
158 | /* | |
159 | * I2C configuration | |
160 | * | |
161 | */ | |
162 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
d0b0dcaa | 163 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
165 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ | |
cd0a9de6 WD |
166 | |
167 | /* | |
168 | * MII PHY configuration | |
169 | * | |
170 | */ | |
96e21f86 | 171 | #define CONFIG_PPC4xx_EMAC |
cd0a9de6 WD |
172 | #define CONFIG_MII 1 /* MII PHY management */ |
173 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
53677ef1 | 174 | #define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ |
cd0a9de6 WD |
175 | /* 32usec min. for LXT971A */ |
176 | #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ | |
177 | ||
178 | /* | |
179 | * RTC configuration | |
180 | * | |
181 | * Note that DS1307 RTC is limited to 100Khz I2C bus. | |
182 | * | |
183 | */ | |
184 | #define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ | |
185 | ||
186 | /* | |
187 | * PCI stuff | |
188 | * | |
189 | */ | |
190 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 191 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
cd0a9de6 WD |
192 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
193 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
194 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
195 | ||
196 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
197 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
198 | /* resource configuration */ | |
199 | #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
200 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
201 | ||
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
203 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
204 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
205 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
206 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
207 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
208 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
209 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
cd0a9de6 WD |
210 | |
211 | /* | |
212 | * IDE stuff | |
213 | * | |
214 | */ | |
215 | #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ | |
216 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
217 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
218 | ||
219 | /* | |
220 | * Environment configuration | |
221 | * | |
222 | */ | |
5a1aceb0 | 223 | #define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ |
9314cee6 | 224 | #undef CONFIG_ENV_IS_IN_NVRAM |
bb1f8b4f | 225 | #undef CONFIG_ENV_IS_IN_EEPROM |
cd0a9de6 WD |
226 | |
227 | /* | |
228 | * General Memory organization | |
229 | * | |
230 | * Start addresses for the final memory configuration | |
231 | * (Set up by the startup code) | |
6d0f6bcf | 232 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
cd0a9de6 | 233 | */ |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
235 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
236 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
14d0a02a | 237 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ |
239 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ | |
240 | ||
241 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE | |
242 | #define CONFIG_SYS_RAMSTART | |
cd0a9de6 WD |
243 | #endif |
244 | ||
5a1aceb0 | 245 | #if defined(CONFIG_ENV_IS_IN_FLASH) |
0e8d1586 JCPV |
246 | #define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ |
247 | #define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ | |
248 | #define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */ | |
249 | #define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ | |
cd0a9de6 WD |
250 | #endif |
251 | ||
252 | /* | |
253 | * FLASH Device configuration | |
254 | * | |
255 | */ | |
6d0f6bcf | 256 | #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ |
00b1883a | 257 | #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
259 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ | |
260 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
261 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ | |
262 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
263 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
cd0a9de6 WD |
264 | |
265 | /* | |
266 | * On Chip Memory location/size | |
267 | * | |
268 | */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
270 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
cd0a9de6 WD |
271 | |
272 | /* | |
273 | * Global info and initial stack | |
274 | * | |
275 | */ | |
6d0f6bcf | 276 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ |
553f0982 | 277 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 278 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 279 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
cd0a9de6 | 280 | |
cd0a9de6 WD |
281 | /* |
282 | * Miscellaneous board specific definitions | |
283 | * | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ |
eeb1b77b | 286 | #define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ |
cd0a9de6 | 287 | |
cd0a9de6 | 288 | #endif /* __CONFIG_H */ |