[people/ms/u-boot.git] / include / configs / cyrus.h

/*
 * Based on corenet_ds.h
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CYRUS

#define CONFIG_PHYS_64BIT

#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif


#define CONFIG_MMC
#define CONFIG_SDCARD
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#ifdef CONFIG_PPC_P5020
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
#endif
#define CONFIG_SYS_DPAA_PME

/*
 * Corenet DS style board configuration file
 */
#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
#if defined(CONFIG_PPC_P5020)
#define CONFIG_SYS_CLK_FREQ 133000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
#elif defined(CONFIG_PPC_P5040)
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
#endif


/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_E500MC			/* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
#define CONFIG_MP			/* support multiple processors */


#define CONFIG_SYS_MMC_MAX_DEVICE     1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xeff40000
#endif

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
#define CONFIG_PCI			/* Enable PCI/PCIE */
#define CONFIG_PCIE1			/* PCIE controler 1 */
#define CONFIG_PCIE2			/* PCIE controler 2 */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_FSL_LAW			/* Use common FSL init code */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_SYS_NO_FLASH

#if defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV          0
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(512 * 1658)
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
#define CONFIG_BTB			/* toggle branch predition */
#define	CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

#define CONFIG_ENABLE_36BIT_PHYS

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
#endif

/* test POST memory test */
#undef CONFIG_POST
#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
#endif
#define CONFIG_SYS_L3_SIZE		(1024 << 10)
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)

#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3

#define CONFIG_SYS_SPD_BUS_NUM	1
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * Local Bus Definitions
 */

#define CONFIG_SYS_LBC0_BASE		0xe0000000 /* Start of LBC Registers */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC0_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_LBC0_BASE_PHYS	CONFIG_SYS_LBC0_BASE
#endif

#define CONFIG_SYS_LBC1_BASE		0xe1000000 /* Start of LBC Registers */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC1_BASE_PHYS	0xfe1000000ull
#else
#define CONFIG_SYS_LBC1_BASE_PHYS	CONFIG_SYS_LBC1_BASE
#endif

/* Set the local bus clock 1/16 of platform clock */
#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_16 | LCRR_EADC_1)

#define CONFIG_SYS_BR0_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)

#define CONFIG_SYS_OR0_PRELIM	0xfff00010
#define CONFIG_SYS_OR1_PRELIM	0xfff00010


#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
#define CONFIG_MISC_INIT_R

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_FSL_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_FSL_I2C_SLAVE		0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET		0x118000
#define CONFIG_SYS_FSL_I2C2_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_FSL_I2C2_SLAVE		0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET		0x118100
#define CONFIG_SYS_FSL_I2C3_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_FSL_I2C3_SLAVE		0x7F
#define CONFIG_SYS_FSL_I2C3_OFFSET		0x119000
#define CONFIG_SYS_FSL_I2C4_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_FSL_I2C4_SLAVE		0x7F
#define CONFIG_SYS_FSL_I2C4_OFFSET		0x119100

#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57

#define CONFIG_SYS_I2C_GENERIC_MAC
#define CONFIG_SYS_I2C_MAC1_BUS 3
#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
#define CONFIG_SYS_I2C_MAC2_BUS 0
#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa

#define CONFIG_CMD_DATE			1
#define CONFIG_RTC_MCP79411		1
#define CONFIG_SYS_RTC_BUS_NUM		3
#define CONFIG_SYS_I2C_RTC_ADDR		0x6f

/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_FSL_ESPI

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
#endif
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
#else
#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */

/* Qman/Bman */
#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					 CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					  CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08

#define CONFIG_SYS_DPAA_FMAN
/* Default address of microcode for the Linux Fman driver */
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)

#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#endif

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_NET_MULTI

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif	/* CONFIG_PCI */

/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif

#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_TBIPA_VALUE	8
#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"FM1@DTSEC4"
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
#endif

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_HAS_FSL_MPH_USB

#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
 /* _VIA_CONTROL_EP  */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif

#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */

#define CONFIG_BAUDRATE	115200

#define __USB_PHY_TYPE	utmi

#define	CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
"bank_intlv=cs0_cs1;"					\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0"						\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
"consoledev=ttyS0\0"					\
"ramdiskaddr=2000000\0"					\
"fdtaddr=c00000\0"					\
"bdev=sda3\0"

#define CONFIG_HDBOOT					\
"setenv bootargs root=/dev/$bdev rw "		\
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $loadaddr $bootfile;"			\
"tftp $fdtaddr $fdtfile;"			\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_NFSBOOTCOMMAND			\
"setenv bootargs root=/dev/nfs rw "	\
"nfsroot=$serverip:$rootpath "		\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $loadaddr $bootfile;"		\
"tftp $fdtaddr $fdtfile;"		\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND				\
"setenv bootargs root=/dev/ram rw "		\
"console=$consoledev,$baudrate $othbootargs;"	\
"tftp $ramdiskaddr $ramdiskfile;"		\
"tftp $loadaddr $bootfile;"			\
"tftp $fdtaddr $fdtfile;"			\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT

#include <asm/fsl_secure_boot.h>

#ifdef CONFIG_SECURE_BOOT
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
87e29878 AF	1	/*
	2	* Based on corenet_ds.h
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
	10	#define CONFIG_DISPLAY_BOARDINFO
	11
	12	#define CONFIG_CYRUS
	13
	14	#define CONFIG_PHYS_64BIT
	15
	16	#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
	17	#error Must call Cyrus CONFIG with a specific CPU enabled.
	18	#endif
	19
	20
	21	#define CONFIG_MMC
	22	#define CONFIG_SDCARD
	23	#define CONFIG_FSL_SATA_V2
	24	#define CONFIG_PCIE3
	25	#define CONFIG_PCIE4
	26	#ifdef CONFIG_PPC_P5020
	27	#define CONFIG_SYS_FSL_RAID_ENGINE
	28	#define CONFIG_SYS_DPAA_RMAN
	29	#endif
	30	#define CONFIG_SYS_DPAA_PME
	31
	32	/*
	33	* Corenet DS style board configuration file
	34	*/
	35	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
	36	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
	37	#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
	38	#if defined(CONFIG_PPC_P5020)
	39	#define CONFIG_SYS_CLK_FREQ 133000000
	40	#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
	41	#elif defined(CONFIG_PPC_P5040)
	42	#define CONFIG_SYS_CLK_FREQ 100000000
	43	#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
	44	#endif
	45
	46
	47	/* High Level Configuration Options */
	48	#define CONFIG_BOOKE
	49	#define CONFIG_E500 /* BOOKE e500 family */
	50	#define CONFIG_E500MC /* BOOKE e500mc family */
	51	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
	52	#define CONFIG_MP /* support multiple processors */
	53
	54
	55	#define CONFIG_SYS_MMC_MAX_DEVICE 1
	56
	57	#ifndef CONFIG_SYS_TEXT_BASE
	58	#define CONFIG_SYS_TEXT_BASE 0xeff40000
	59	#endif
	60
	61	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
	62	#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
	63	#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
	64	#define CONFIG_PCI /* Enable PCI/PCIE */
65	#define CONFIG_PCIE1 /* PCIE controler 1 */
66	#define CONFIG_PCIE2 /* PCIE controler 2 */
67	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
68	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
69
70	#define CONFIG_FSL_LAW /* Use common FSL init code */
71
72	#define CONFIG_ENV_OVERWRITE
73
74	#define CONFIG_SYS_NO_FLASH
75
76	#if defined(CONFIG_SDCARD)
77	#define CONFIG_SYS_EXTRA_ENV_RELOC
78	#define CONFIG_ENV_IS_IN_MMC
79	#define CONFIG_FSL_FIXED_MMC_LOCATION
80	#define CONFIG_SYS_MMC_ENV_DEV 0
81	#define CONFIG_ENV_SIZE 0x2000
82	#define CONFIG_ENV_OFFSET (512 * 1658)
83	#endif
84
85	/*
86	* These can be toggled for performance analysis, otherwise use default.
87	*/
88	#define CONFIG_SYS_CACHE_STASHING
89	#define CONFIG_BACKSIDE_L2_CACHE
90	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
91	#define CONFIG_BTB /* toggle branch predition */
92	#define CONFIG_DDR_ECC
93	#ifdef CONFIG_DDR_ECC
94	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
95	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
96	#endif
97
98	#define CONFIG_ENABLE_36BIT_PHYS
99
100	#ifdef CONFIG_PHYS_64BIT
101	#define CONFIG_ADDR_MAP
102	#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
103	#endif
104
105	/* test POST memory test */
106	#undef CONFIG_POST
107	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
108	#define CONFIG_SYS_MEMTEST_END 0x00400000
109	#define CONFIG_SYS_ALT_MEMTEST
110	#define CONFIG_PANIC_HANG /* do not reset board on panic */
111
112	/*
113	* Config the L3 Cache as L3 SRAM
114	*/
115	#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
116	#ifdef CONFIG_PHYS_64BIT
117	#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull \| CONFIG_RAMBOOT_TEXT_BASE)
118	#else
119	#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
120	#endif
121	#define CONFIG_SYS_L3_SIZE (1024 << 10)
122	#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
123
124	#ifdef CONFIG_PHYS_64BIT
125	#define CONFIG_SYS_DCSRBAR 0xf0000000
126	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
127	#endif
128
129	/*
130	* DDR Setup
131	*/
132	#define CONFIG_VERY_BIG_RAM
133	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
134	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
135
136	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
137	#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
138
139	#define CONFIG_DDR_SPD
140	#define CONFIG_SYS_FSL_DDR3
141
142	#define CONFIG_SYS_SPD_BUS_NUM 1
143	#define SPD_EEPROM_ADDRESS1 0x51
144	#define SPD_EEPROM_ADDRESS2 0x52
145	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
146
147	/*
148	* Local Bus Definitions
149	*/
150
151	#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
152	#ifdef CONFIG_PHYS_64BIT
153	#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
154	#else
155	#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
156	#endif
157
158	#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
159	#ifdef CONFIG_PHYS_64BIT
160	#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
161	#else
162	#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
163	#endif
164
165	/* Set the local bus clock 1/16 of platform clock */
166	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 \| LCRR_EADC_1)
167
168	#define CONFIG_SYS_BR0_PRELIM \
169	(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) \| BR_PS_16 \| BR_V)
170	#define CONFIG_SYS_BR1_PRELIM \
171	(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) \| BR_PS_16 \| BR_V)
172
173	#define CONFIG_SYS_OR0_PRELIM 0xfff00010
174	#define CONFIG_SYS_OR1_PRELIM 0xfff00010
175
176
177	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
178
179	#if defined(CONFIG_RAMBOOT_PBL)
180	#define CONFIG_SYS_RAMBOOT
181	#endif
182
183	#define CONFIG_BOARD_EARLY_INIT_F
184	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
185	#define CONFIG_MISC_INIT_R
186
187	#define CONFIG_HWCONFIG
188
189	/* define to use L1 as initial stack */
190	#define CONFIG_L1_INIT_RAM
191	#define CONFIG_SYS_INIT_RAM_LOCK
192	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
193	#ifdef CONFIG_PHYS_64BIT
194	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
195	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
196	/* The assembler doesn't like typecast */
197	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
198	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
199	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
200	#else
201	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
202	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
203	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
204	#endif
205	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
206
207	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
211	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
212
213	/* Serial Port - controlled on board with jumper J8
214	* open - index 2
215	* shorted - index 1
216	*/
217	#define CONFIG_CONS_INDEX 1
87e29878 AF	218	#define CONFIG_SYS_NS16550_SERIAL
	219	#define CONFIG_SYS_NS16550_REG_SIZE 1
	220	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	221
	222	#define CONFIG_SYS_BAUDRATE_TABLE \
	223	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	224
	225	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	226	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	227	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	228	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	229
	230	/* Use the HUSH parser */
	231	#define CONFIG_SYS_HUSH_PARSER
	232	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	233
	234	/* pass open firmware flat tree */
	235	#define CONFIG_OF_LIBFDT
	236	#define CONFIG_OF_BOARD_SETUP
	237
	238	/* new uImage format support */
	239	#define CONFIG_FIT
	240	#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
	241
	242	/* I2C */
	243	#define CONFIG_SYS_I2C
	244	#define CONFIG_SYS_I2C_FSL
	245	#define CONFIG_I2C_MULTI_BUS
	246	#define CONFIG_I2C_CMD_TREE
	247	#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
	248	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	249	#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
	250	#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
	251	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	252	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
	253	#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
	254	#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
	255	#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
	256	#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
	257	#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
	258	#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
	259
	260	#define CONFIG_ID_EEPROM
	261	#define CONFIG_SYS_I2C_EEPROM_NXID
	262	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	263	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	264	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	265
	266	#define CONFIG_SYS_I2C_GENERIC_MAC
	267	#define CONFIG_SYS_I2C_MAC1_BUS 3
	268	#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
	269	#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
	270	#define CONFIG_SYS_I2C_MAC2_BUS 0
	271	#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
	272	#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
	273
	274	#define CONFIG_CMD_DATE 1
	275	#define CONFIG_RTC_MCP79411 1
	276	#define CONFIG_SYS_RTC_BUS_NUM 3
	277	#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
	278
	279	/*
	280	* eSPI - Enhanced SPI
	281	*/
282	#define CONFIG_FSL_ESPI
283
284	/*
285	* General PCI
286	* Memory space is mapped 1-1, but I/O space must start from 0.
287	*/
288
289	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
290	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
291	#ifdef CONFIG_PHYS_64BIT
292	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
293	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
294	#else
295	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
296	#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
297	#endif
298	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
299	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
300	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
301	#ifdef CONFIG_PHYS_64BIT
302	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
303	#else
304	#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
305	#endif
306	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
307
308	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
309	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
310	#ifdef CONFIG_PHYS_64BIT
311	#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
312	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
313	#else
314	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
315	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
316	#endif
317	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
318	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
319	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
320	#ifdef CONFIG_PHYS_64BIT
321	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
322	#else
323	#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
324	#endif
325	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
326
327	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
328	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
329	#ifdef CONFIG_PHYS_64BIT
330	#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
331	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
332	#else
333	#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
334	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
335	#endif
336	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
337	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
338	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
339	#ifdef CONFIG_PHYS_64BIT
340	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
341	#else
342	#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
343	#endif
344	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
345
346	/* controller 4, Base address 203000 */
347	#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
348	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
349	#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
350	#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
351	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
352	#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
353
354	/* Qman/Bman */
355	#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
356	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
357	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
358	#ifdef CONFIG_PHYS_64BIT
359	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
360	#else
361	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
362	#endif
363	#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
364	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
365	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
366	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
367	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
368	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
369	CONFIG_SYS_BMAN_CENA_SIZE)
370	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
371	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
372	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
373	#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
374	#ifdef CONFIG_PHYS_64BIT
375	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
376	#else
377	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
378	#endif
379	#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
380	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
381	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
382	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
383	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
384	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
385	CONFIG_SYS_QMAN_CENA_SIZE)
386	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
387	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
388
389	#define CONFIG_SYS_DPAA_FMAN
390	/* Default address of microcode for the Linux Fman driver */
391	/*
392	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
393	* about 825KB (1650 blocks), Env is stored after the image, and the env size is
394	* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
395	*/
396	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
397	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
398
399	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
400	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
401
402	#ifdef CONFIG_SYS_DPAA_FMAN
403	#define CONFIG_FMAN_ENET
404	#define CONFIG_PHY_MICREL
405	#define CONFIG_PHY_MICREL_KSZ9021
406	#endif
407
408	#ifdef CONFIG_PCI
409	#define CONFIG_PCI_INDIRECT_BRIDGE
410	#define CONFIG_PCI_PNP /* do pci plug-and-play */
411	#define CONFIG_NET_MULTI
412
413	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
414	#define CONFIG_DOS_PARTITION
415	#endif /* CONFIG_PCI */
416
417	/* SATA */
418	#ifdef CONFIG_FSL_SATA_V2
419	#define CONFIG_LIBATA
420	#define CONFIG_FSL_SATA
421
422	#define CONFIG_SYS_SATA_MAX_DEVICE 2
423	#define CONFIG_SATA1
424	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
425	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
426	#define CONFIG_SATA2
427	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
428	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
429
430	#define CONFIG_LBA48
431	#define CONFIG_CMD_SATA
432	#define CONFIG_DOS_PARTITION
433	#define CONFIG_CMD_EXT2
434	#endif
435
436	#ifdef CONFIG_FMAN_ENET
437	#define CONFIG_SYS_TBIPA_VALUE 8
438	#define CONFIG_MII /* MII PHY management */
439	#define CONFIG_ETHPRIME "FM1@DTSEC4"
440	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
441	#endif
442
443	/*
444	* Environment
445	*/
446	#define CONFIG_LOADS_ECHO /* echo on for serial download */
447	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
448
449	/*
450	* Command line configuration.
451	*/
452	#define CONFIG_CMD_DHCP
453	#define CONFIG_CMD_ERRATA
454	#define CONFIG_CMD_GREPENV
455	#define CONFIG_CMD_IRQ
456	#define CONFIG_CMD_I2C
457	#define CONFIG_CMD_MII
458	#define CONFIG_CMD_PING
459	#define CONFIG_CMD_REGINFO
460
461	#ifdef CONFIG_PCI
462	#define CONFIG_CMD_PCI
463	#endif
464
465	/*
466	* USB
467	*/
468	#define CONFIG_HAS_FSL_DR_USB
469	#define CONFIG_HAS_FSL_MPH_USB
470
471	#if defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB)
472	#define CONFIG_CMD_USB
473	#define CONFIG_USB_STORAGE
474	#define CONFIG_USB_EHCI
475	#define CONFIG_USB_EHCI_FSL
476	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
477	#define CONFIG_CMD_EXT2
478	#define CONFIG_EHCI_IS_TDI
479	#define CONFIG_USB_KEYBOARD
480	#define CONFIG_SYS_USB_EVENT_POLL
481	/* _VIA_CONTROL_EP */
482	#define CONFIG_CONSOLE_MUX
483	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
484	#endif
485
486	#ifdef CONFIG_MMC
487	#define CONFIG_FSL_ESDHC
488	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
489	#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
490	#define CONFIG_CMD_MMC
491	#define CONFIG_GENERIC_MMC
492	#define CONFIG_CMD_EXT2
493	#define CONFIG_CMD_FAT
494	#define CONFIG_DOS_PARTITION
495	#endif
496
497	/*
498	* Miscellaneous configurable options
499	*/
500	#define CONFIG_SYS_LONGHELP /* undef to save memory */
501	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
502	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
503	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
504	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
505	#ifdef CONFIG_CMD_KGDB
506	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
507	#else
508	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
509	#endif
510	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
511	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
512	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
513
514	/*
515	* For booting Linux, the board info and command line data
516	* have to be in the first 64 MB of memory, since this is
517	* the maximum mapped by the Linux kernel during initialization.
518	*/
519	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
520	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
521
522	#ifdef CONFIG_CMD_KGDB
523	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
524	#endif
525
526	/*
527	* Environment Configuration
528	*/
529	#define CONFIG_ROOTPATH "/opt/nfsroot"
530	#define CONFIG_BOOTFILE "uImage"
531	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
532
533	/* default location for tftp and bootm */
534	#define CONFIG_LOADADDR 1000000
535
536	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
537
538	#define CONFIG_BAUDRATE 115200
539
540	#define __USB_PHY_TYPE utmi
541
542	#define CONFIG_EXTRA_ENV_SETTINGS \
543	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
544	"bank_intlv=cs0_cs1;" \
545	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
546	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
547	"netdev=eth0\0" \
548	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
549	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
550	"consoledev=ttyS0\0" \
551	"ramdiskaddr=2000000\0" \
552	"fdtaddr=c00000\0" \
553	"bdev=sda3\0"
554
555	#define CONFIG_HDBOOT \
556	"setenv bootargs root=/dev/$bdev rw " \
557	"console=$consoledev,$baudrate $othbootargs;" \
558	"tftp $loadaddr $bootfile;" \
559	"tftp $fdtaddr $fdtfile;" \
560	"bootm $loadaddr - $fdtaddr"
561
562	#define CONFIG_NFSBOOTCOMMAND \
563	"setenv bootargs root=/dev/nfs rw " \
564	"nfsroot=$serverip:$rootpath " \
565	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
566	"console=$consoledev,$baudrate $othbootargs;" \
567	"tftp $loadaddr $bootfile;" \
568	"tftp $fdtaddr $fdtfile;" \
569	"bootm $loadaddr - $fdtaddr"
570
571	#define CONFIG_RAMBOOTCOMMAND \
572	"setenv bootargs root=/dev/ram rw " \
573	"console=$consoledev,$baudrate $othbootargs;" \
574	"tftp $ramdiskaddr $ramdiskfile;" \
575	"tftp $loadaddr $bootfile;" \
576	"tftp $fdtaddr $fdtfile;" \
577	"bootm $loadaddr $ramdiskaddr $fdtaddr"
578
579	#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
580
581	#include <asm/fsl_secure_boot.h>
582
583	#ifdef CONFIG_SECURE_BOOT
584	#endif
585
586	#endif /* __CONFIG_H */