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89b765c7 SR |
1 | /* |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | ||
26 | /* | |
27 | * Board | |
28 | */ | |
29 | ||
30 | /* | |
31 | * SoC Configuration | |
32 | */ | |
33 | #define CONFIG_MACH_DAVINCI_DA850_EVM | |
34 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ | |
35 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ | |
36 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
37 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
38 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
39 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
40 | #define CONFIG_SYS_HZ 1000 | |
41 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
89b765c7 SR |
42 | |
43 | /* | |
44 | * Memory Info | |
45 | */ | |
46 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
47 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ | |
48 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
49 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
97003756 | 50 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
89b765c7 SR |
51 | |
52 | /* memtest start addr */ | |
53 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
54 | ||
55 | /* memtest will be run on 16MB */ | |
56 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
57 | ||
58 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
59 | #define CONFIG_STACKSIZE (256*1024) /* regular stack */ | |
60 | ||
61 | /* | |
62 | * Serial Driver info | |
63 | */ | |
64 | #define CONFIG_SYS_NS16550 | |
65 | #define CONFIG_SYS_NS16550_SERIAL | |
66 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
67 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
68 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
69 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
70 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
71 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
72 | ||
73 | /* | |
74 | * I2C Configuration | |
75 | */ | |
76 | #define CONFIG_HARD_I2C | |
77 | #define CONFIG_DRIVER_DAVINCI_I2C | |
78 | #define CONFIG_SYS_I2C_SPEED 25000 | |
79 | #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
80 | ||
6b2c6468 BG |
81 | /* |
82 | * Flash & Environment | |
83 | */ | |
84 | #ifdef CONFIG_USE_NAND | |
85 | #undef CONFIG_ENV_IS_IN_FLASH | |
86 | #define CONFIG_NAND_DAVINCI | |
87 | #define CONFIG_SYS_NO_FLASH | |
88 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ | |
89 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ | |
90 | #define CONFIG_ENV_SIZE (128 << 10) | |
91 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
92 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
93 | #define CONFIG_SYS_NAND_PAGE_2K | |
94 | #define CONFIG_SYS_NAND_CS 3 | |
95 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
96 | #define CONFIG_SYS_CLE_MASK 0x10 | |
97 | #define CONFIG_SYS_ALE_MASK 0x8 | |
98 | #undef CONFIG_SYS_NAND_HW_ECC | |
99 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
100 | #define NAND_MAX_CHIPS 1 | |
101 | #define DEF_BOOTM "" | |
102 | #endif | |
103 | ||
89b765c7 SR |
104 | /* |
105 | * U-Boot general configuration | |
106 | */ | |
107 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
108 | #define CONFIG_SYS_PROMPT "DA850-evm > " /* Command Prompt */ | |
109 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
110 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
111 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
112 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
113 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
114 | #define CONFIG_VERSION_VARIABLE | |
115 | #define CONFIG_AUTO_COMPLETE | |
116 | #define CONFIG_SYS_HUSH_PARSER | |
117 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
118 | #define CONFIG_CMDLINE_EDITING | |
119 | #define CONFIG_SYS_LONGHELP | |
120 | #define CONFIG_CRC32_VERIFY | |
121 | #define CONFIG_MX_CYCLIC | |
122 | ||
123 | /* | |
124 | * Linux Information | |
125 | */ | |
126 | #define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) | |
127 | #define CONFIG_CMDLINE_TAG | |
128 | #define CONFIG_SETUP_MEMORY_TAGS | |
129 | #define CONFIG_BOOTARGS \ | |
130 | "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" | |
131 | #define CONFIG_BOOTDELAY 3 | |
132 | ||
133 | /* | |
134 | * U-Boot commands | |
135 | */ | |
136 | #include <config_cmd_default.h> | |
137 | #define CONFIG_CMD_ENV | |
138 | #define CONFIG_CMD_ASKENV | |
139 | #define CONFIG_CMD_DHCP | |
140 | #define CONFIG_CMD_DIAG | |
141 | #define CONFIG_CMD_MII | |
142 | #define CONFIG_CMD_PING | |
143 | #define CONFIG_CMD_SAVES | |
144 | #define CONFIG_CMD_MEMORY | |
145 | ||
146 | #ifndef CONFIG_DRIVER_TI_EMAC | |
147 | #undef CONFIG_CMD_NET | |
148 | #undef CONFIG_CMD_DHCP | |
149 | #undef CONFIG_CMD_MII | |
150 | #undef CONFIG_CMD_PING | |
151 | #endif | |
152 | ||
6b2c6468 BG |
153 | #ifdef CONFIG_USE_NAND |
154 | #undef CONFIG_CMD_FLASH | |
155 | #undef CONFIG_CMD_IMLS | |
156 | #define CONFIG_CMD_NAND | |
157 | #endif | |
158 | ||
89b765c7 SR |
159 | #if !defined(CONFIG_USE_NAND) && \ |
160 | !defined(CONFIG_USE_NOR) && \ | |
161 | !defined(CONFIG_USE_SPIFLASH) | |
162 | #define CONFIG_ENV_IS_NOWHERE | |
163 | #define CONFIG_SYS_NO_FLASH | |
164 | #define CONFIG_ENV_SIZE (16 << 10) | |
165 | #undef CONFIG_CMD_IMLS | |
166 | #undef CONFIG_CMD_ENV | |
167 | #endif | |
168 | ||
ab86f72c | 169 | /* additions for new relocation code, must added to all boards */ |
ab86f72c HS |
170 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
171 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ | |
172 | CONFIG_SYS_GBL_DATA_SIZE) | |
89b765c7 | 173 | #endif /* __CONFIG_H */ |