[people/ms/u-boot.git] / include / configs / da850evm.h

/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
#define CONFIG_DRIVER_TI_EMAC
/* check if direct NOR boot config is used */
#ifndef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_USE_SPIFLASH
#endif

/*
* Disable DM_* for SPL build and can be re-enabled after adding
* DM support in SPL
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_DM_I2C
#undef CONFIG_DM_I2C_COMPAT
#endif
/*
 * SoC Configuration
 */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
#endif

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)

#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */

#define CONFIG_SYS_DA850_PLL0_PLLM     24
#define CONFIG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
#endif
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */

#define CONFIG_SPI
#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
#endif

#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
#endif

/*
 * I2C Configuration
 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
#endif

/*
 * Flash & Environment
 */
#ifdef CONFIG_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE			(128 << 10)
#define	CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE		0x10
#define CONFIG_SYS_NAND_MASK_ALE		0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x28000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
				24, 25, 26, 27, 28, \
				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
				59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_LOAD
#endif

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

#ifdef CONFIG_USE_NOR
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	       + 3)
#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
#endif

#ifdef CONFIG_USE_SPIFLASH
#define CONFIG_ENV_SIZE			(64 << 10)
#define CONFIG_ENV_OFFSET		(512 << 10)
#define CONFIG_ENV_SECT_SIZE		(64 << 10)
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SPI_FLASH_MTD
#endif
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG		/* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS

#define CONFIG_BOOTCOMMAND \
		"run envboot; " \
		"run mmcboot; "

#define DEFAULT_LINUX_BOOT_ENV \
	"loadaddr=0xc0700000\0" \
	"fdtaddr=0xc0600000\0" \
	"scriptaddr=0xc0600000\0"

#include <environment/ti/mmc.h>

#define CONFIG_EXTRA_ENV_SETTINGS \
	DEFAULT_LINUX_BOOT_ENV \
	DEFAULT_MMC_TI_ARGS \
	"bootpart=0:2\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"fdtfile=da850-evm.dtb\0" \
	"boot_fdt=yes\0" \
	"boot_fit=0\0" \
	"console=ttyS2,115200n8\0" \
	"hwconfig=dsp:wake=yes"

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#ifdef CONFIG_USE_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif

#if !defined(CONFIG_USE_NAND) && \
	!defined(CONFIG_USE_NOR) && \
	!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_SIZE		(16 << 10)
#endif

#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_TEXT_BASE	0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT	32768
#define CONFIG_SPL_PAD_TO	32768
#endif

/* Load U-Boot Image From MMC */
#ifdef CONFIG_SPL_MMC_LOAD
#undef CONFIG_SPL_SPI_LOAD
#endif

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000

#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_SYS_INIT_SP_ADDR		0x8001ff00
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
					GENERATED_GBL_DATA_SIZE)
#endif /* CONFIG_DIRECT_NOR_BOOT */

#include <asm/arch/hardware.h>

#endif /* __CONFIG_H */
Commit	Line	Data
89b765c7 SR	1	/*
	2	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* Based on davinci_dvevm.h. Original Copyrights follow:
	5	*
	6	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
89b765c7 SR	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* Board
	16	*/
3d248d37	17	#define CONFIG_DRIVER_TI_EMAC
63777665 LP	18	/* check if direct NOR boot config is used */
63777665 LP	19	#ifndef CONFIG_DIRECT_NOR_BOOT
d73a8a1b	20	#define CONFIG_USE_SPIFLASH
63777665	21	#endif
89b765c7	22
a4670f8e AF	23	/*
	24	* Disable DM_* for SPL build and can be re-enabled after adding
	25	* DM support in SPL
	26	*/
	27	#ifdef CONFIG_SPL_BUILD
	28	#undef CONFIG_DM_SPI
	29	#undef CONFIG_DM_SPI_FLASH
	30	#undef CONFIG_DM_I2C
	31	#undef CONFIG_DM_I2C_COMPAT
	32	#endif
89b765c7 SR	33	/*
	34	* SoC Configuration
	35	*/
b67d8816	36	#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
89b765c7 SR	37	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	38	#define CONFIG_SYS_OSCIN_FREQ 24000000
	39	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	40	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
89b765c7	41
63777665 LP	42	#ifdef CONFIG_DIRECT_NOR_BOOT
	43	#define CONFIG_ARCH_CPU_INIT
	44	#define CONFIG_DA8XX_GPIO
63777665	45	#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
63777665 LP	46	#endif
63777665 LP	47
89b765c7 SR	48	/*
	49	* Memory Info
	50	*/
	51	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
89b765c7 SR	52	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
89b765c7 SR	53	#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
97003756	54	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
89b765c7 SR	55
	56	/* memtest start addr */
	57	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
	58
	59	/* memtest will be run on 16MB */
	60	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 1610241024)
	61
	62	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
89b765c7	63
3d2c8e6c CR	64	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	65	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	66	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	67	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	68	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	69	DAVINCI_SYSCFG_SUSPSRC_I2C)
	70
	71	/*
	72	* PLL configuration
	73	*/
3d2c8e6c CR	74
	75	#define CONFIG_SYS_DA850_PLL0_PLLM 24
	76	#define CONFIG_SYS_DA850_PLL1_PLLM 21
	77
	78	/*
	79	* DDR2 memory configuration
	80	*/
	81	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	82	DV_DDR_PHY_EXT_STRBEN \| \
	83	(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	84
	85	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	86	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) \| \
	87	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	88	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	89	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	90	(0x3 << DV_DDR_SDCR_CL_SHIFT) \| \
	91	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	92	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	93
	94	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	95	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	96
	97	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	98	(14 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	99	(2 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	100	(2 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	101	(1 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	102	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	103	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	104	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	105	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
	106
	107	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	108	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	109	(0 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	110	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
	111	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
	112	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	113	(0 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	114	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
	115
	116	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
	117	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
	118
89b765c7 SR	119	/*
	120	* Serial Driver info
	121	*/
a4670f8e AF	122
a4670f8e AF	123	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_DIRECT_NOR_BOOT)
89b765c7 SR	124	#define CONFIG_SYS_NS16550_SERIAL
	125	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
	126	#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
a4670f8e	127	#endif
89b765c7 SR	128	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
89b765c7 SR	129	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
89b765c7	130
d73a8a1b	131	#define CONFIG_SPI
d73a8a1b	132	#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
a4670f8e AF	133	#ifdef CONFIG_SPL_BUILD
a4670f8e AF	134	#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
d73a8a1b SB	135	#define CONFIG_SF_DEFAULT_SPEED 30000000
d73a8a1b SB	136	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
a4670f8e	137	#endif
d73a8a1b	138
42612104	139	#ifdef CONFIG_USE_SPIFLASH
42612104	140	#define CONFIG_SPL_SPI_LOAD
42612104	141	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
2a10f8b9	142	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
42612104 LP	143	#endif
42612104 LP	144
89b765c7 SR	145	/*
	146	* I2C Configuration
	147	*/
c774207f	148	#ifndef CONFIG_SPL_BUILD
e8459dcc	149	#define CONFIG_SYS_I2C_DAVINCI
d2607401	150	#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
c774207f	151	#endif
89b765c7	152
6b2c6468 BG	153	/*
	154	* Flash & Environment
	155	*/
	156	#ifdef CONFIG_USE_NAND
6b2c6468	157	#define CONFIG_NAND_DAVINCI
6b2c6468 BG	158	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
	159	#define CONFIG_ENV_SIZE (128 << 10)
	160	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	161	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	162	#define CONFIG_SYS_NAND_PAGE_2K
	163	#define CONFIG_SYS_NAND_CS 3
	164	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
34fa0706 EB	165	#define CONFIG_SYS_NAND_MASK_CLE 0x10
34fa0706 EB	166	#define CONFIG_SYS_NAND_MASK_ALE 0x8
6b2c6468 BG	167	#undef CONFIG_SYS_NAND_HW_ECC
6b2c6468 BG	168	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
122f9c9b LP	169	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
	170	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	171	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	172	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
	173	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
	174	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
	175	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	176	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	177	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	178	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	179	CONFIG_SYS_MALLOC_LEN - \
	180	GENERATED_GBL_DATA_SIZE)
	181	#define CONFIG_SYS_NAND_ECCPOS { \
	182	24, 25, 26, 27, 28, \
	183	29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
	184	39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
	185	49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
	186	59, 60, 61, 62, 63 }
	187	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	188	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	189	#define CONFIG_SYS_NAND_ECCSIZE 512
	190	#define CONFIG_SYS_NAND_ECCBYTES 10
	191	#define CONFIG_SYS_NAND_OOBSIZE 64
6f2f01b9 SW	192	#define CONFIG_SPL_NAND_BASE
	193	#define CONFIG_SPL_NAND_DRIVERS
	194	#define CONFIG_SPL_NAND_ECC
122f9c9b	195	#define CONFIG_SPL_NAND_LOAD
6b2c6468 BG	196	#endif
6b2c6468 BG	197
3d248d37 BG	198	/*
	199	* Network & Ethernet Configuration
	200	*/
	201	#ifdef CONFIG_DRIVER_TI_EMAC
3d248d37	202	#define CONFIG_MII
3d248d37 BG	203	#define CONFIG_BOOTP_DNS2
	204	#define CONFIG_BOOTP_SEND_HOSTNAME
	205	#define CONFIG_NET_RETRY_COUNT 10
3d248d37 BG	206	#endif
3d248d37 BG	207
1506b0a8	208	#ifdef CONFIG_USE_NOR
1506b0a8 NN	209	#define CONFIG_FLASH_CFI_DRIVER
	210	#define CONFIG_SYS_FLASH_CFI
	211	#define CONFIG_SYS_FLASH_PROTECTION
	212	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	213	#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
	214	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
	215	#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
	216	#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
	217	#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
	218	#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
	219	+ 3)
	220	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
	221	#endif
	222
d73a8a1b	223	#ifdef CONFIG_USE_SPIFLASH
d73a8a1b	224	#define CONFIG_ENV_SIZE (64 << 10)
2a10f8b9	225	#define CONFIG_ENV_OFFSET (512 << 10)
d73a8a1b	226	#define CONFIG_ENV_SECT_SIZE (64 << 10)
f4fad716 AF	227	#ifdef CONFIG_SPL_BUILD
	228	#undef CONFIG_SPI_FLASH_MTD
	229	#endif
	230	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	231	#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
d73a8a1b SB	232	#endif
d73a8a1b SB	233
89b765c7 SR	234	/*
	235	* U-Boot general configuration
	236	*/
cf2c24e3	237	#define CONFIG_MISC_INIT_R
89b765c7	238	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
89b765c7	239	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
89b765c7 SR	240	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
89b765c7 SR	241	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
89b765c7 SR	242	#define CONFIG_MX_CYCLIC
	243
	244	/*
	245	* Linux Information
	246	*/
59e0d611	247	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
cf2c24e3	248	#define CONFIG_HWCONFIG /* enable hwconfig */
89b765c7	249	#define CONFIG_CMDLINE_TAG
4f6fc15b	250	#define CONFIG_REVISION_TAG
89b765c7	251	#define CONFIG_SETUP_MEMORY_TAGS
a4670f8e AF	252
	253	#define CONFIG_BOOTCOMMAND \
	254	"run envboot; " \
	255	"run mmcboot; "
	256
	257	#define DEFAULT_LINUX_BOOT_ENV \
	258	"loadaddr=0xc0700000\0" \
	259	"fdtaddr=0xc0600000\0" \
	260	"scriptaddr=0xc0600000\0"
	261
	262	#include <environment/ti/mmc.h>
	263
	264	#define CONFIG_EXTRA_ENV_SETTINGS \
	265	DEFAULT_LINUX_BOOT_ENV \
	266	DEFAULT_MMC_TI_ARGS \
	267	"bootpart=0:2\0" \
	268	"bootdir=/boot\0" \
	269	"bootfile=zImage\0" \
	270	"fdtfile=da850-evm.dtb\0" \
	271	"boot_fdt=yes\0" \
	272	"boot_fit=0\0" \
	273	"console=ttyS2,115200n8\0" \
	274	"hwconfig=dsp:wake=yes"
89b765c7	275
8f5d4687 HM	276	#ifdef CONFIG_CMD_BDI
	277	#define CONFIG_CLOCKS
	278	#endif
	279
6b2c6468	280	#ifdef CONFIG_USE_NAND
771d028a BG	281	#define CONFIG_MTD_DEVICE
771d028a BG	282	#define CONFIG_MTD_PARTITIONS
6b2c6468 BG	283	#endif
6b2c6468 BG	284
89b765c7 SR	285	#if !defined(CONFIG_USE_NAND) && \
	286	!defined(CONFIG_USE_NOR) && \
	287	!defined(CONFIG_USE_SPIFLASH)
89b765c7	288	#define CONFIG_ENV_SIZE (16 << 10)
89b765c7 SR	289	#endif
89b765c7 SR	290
63777665	291	#ifndef CONFIG_DIRECT_NOR_BOOT
3d2c8e6c	292	/* defines for SPL */
3f7f2414 TR	293	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	294	CONFIG_SYS_MALLOC_LEN)
	295	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
3f7f2414	296	#define CONFIG_SPL_SPI_LOAD
3d2c8e6c CR	297	#define CONFIG_SPL_STACK 0x8001ff00
3d2c8e6c CR	298	#define CONFIG_SPL_TEXT_BASE 0x80000000
b7b5f1a1	299	#define CONFIG_SPL_MAX_FOOTPRINT 32768
532d5318	300	#define CONFIG_SPL_PAD_TO 32768
63777665	301	#endif
0d986e61 LP	302
	303	/* Load U-Boot Image From MMC */
	304	#ifdef CONFIG_SPL_MMC_LOAD
0d986e61 LP	305	#undef CONFIG_SPL_SPI_LOAD
	306	#endif
	307
ab86f72c	308	/* additions for new relocation code, must added to all boards */
ab86f72c	309	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
63777665 LP	310
	311	#ifdef CONFIG_DIRECT_NOR_BOOT
	312	#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
	313	#else
ab86f72c	314	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
25ddd1fb	315	GENERATED_GBL_DATA_SIZE)
63777665	316	#endif /* CONFIG_DIRECT_NOR_BOOT */
89f5eaa1 SG	317
	318	#include <asm/arch/hardware.h>
	319
89b765c7	320	#endif /* __CONFIG_H */