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2d4072c0 | 1 | /* |
a4474ff8 | 2 | * Copyright (C) 2009 Texas Instruments Incorporated |
2d4072c0 SP |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
2d4072c0 SP |
22 | |
23 | /* Spectrum Digital TMS320DM365 EVM board */ | |
24 | #define DAVINCI_DM365EVM | |
25 | ||
26 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ | |
27 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
28 | #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ | |
29 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
30 | ||
31 | /* SoC Configuration */ | |
32 | #define CONFIG_ARM926EJS /* arm926ejs CPU */ | |
33 | #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ | |
34 | #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ | |
35 | #define CONFIG_SYS_HZ 1000 | |
36 | #define CONFIG_SOC_DM365 | |
37 | ||
38 | /* Memory Info */ | |
39 | #define CONFIG_NR_DRAM_BANKS 1 | |
40 | #define PHYS_SDRAM_1 0x80000000 | |
a16df2c1 | 41 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ |
2d4072c0 SP |
42 | |
43 | /* Serial Driver info: UART0 for console */ | |
44 | #define CONFIG_SYS_NS16550 | |
45 | #define CONFIG_SYS_NS16550_SERIAL | |
46 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
47 | #define CONFIG_SYS_NS16550_COM1 0x01c20000 | |
48 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK | |
49 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
50 | #define CONFIG_CONS_INDEX 1 | |
51 | #define CONFIG_BAUDRATE 115200 | |
52 | ||
53 | /* EEPROM definitions for EEPROM on DM365 EVM */ | |
54 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
55 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
56 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
57 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
58 | ||
59 | /* Network Configuration */ | |
60 | #define CONFIG_DRIVER_TI_EMAC | |
61 | #define CONFIG_MII | |
62 | #define CONFIG_BOOTP_DEFAULT | |
63 | #define CONFIG_BOOTP_DNS | |
64 | #define CONFIG_BOOTP_DNS2 | |
65 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
66 | #define CONFIG_NET_RETRY_COUNT 10 | |
67 | #define CONFIG_NET_MULTI | |
68 | ||
69 | /* I2C */ | |
70 | #define CONFIG_HARD_I2C | |
71 | #define CONFIG_DRIVER_DAVINCI_I2C | |
72 | #define CONFIG_SYS_I2C_SPEED 400000 | |
73 | #define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ | |
74 | ||
75 | /* NAND: socketed, two chipselects, normally 2 GBytes */ | |
76 | #define CONFIG_NAND_DAVINCI | |
97f4eb8c | 77 | #define CONFIG_SYS_NAND_CS 2 |
2d4072c0 SP |
78 | #define CONFIG_SYS_NAND_USE_FLASH_BBT |
79 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
80 | #define CONFIG_SYS_NAND_PAGE_2K | |
81 | ||
82 | #define CONFIG_SYS_NAND_LARGEPAGE | |
83 | #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } | |
84 | /* socket has two chipselects, nCE0 gated by address BIT(14) */ | |
85 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
86 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
87 | ||
88 | /* U-Boot command configuration */ | |
89 | #include <config_cmd_default.h> | |
90 | ||
91 | #undef CONFIG_CMD_BDI | |
92 | #undef CONFIG_CMD_FLASH | |
93 | #undef CONFIG_CMD_FPGA | |
94 | #undef CONFIG_CMD_SETGETDCR | |
95 | ||
96 | #define CONFIG_CMD_ASKENV | |
97 | #define CONFIG_CMD_DHCP | |
98 | #define CONFIG_CMD_I2C | |
99 | #define CONFIG_CMD_PING | |
100 | #define CONFIG_CMD_SAVES | |
2d4072c0 SP |
101 | |
102 | #ifdef CONFIG_NAND_DAVINCI | |
103 | #define CONFIG_CMD_MTDPARTS | |
104 | #define CONFIG_MTD_PARTITIONS | |
105 | #define CONFIG_MTD_DEVICE | |
106 | #define CONFIG_CMD_NAND | |
107 | #define CONFIG_CMD_UBI | |
108 | #define CONFIG_RBTREE | |
109 | #endif | |
110 | ||
111 | #define CONFIG_CRC32_VERIFY | |
112 | #define CONFIG_MX_CYCLIC | |
113 | ||
114 | /* U-Boot general configuration */ | |
115 | #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ | |
116 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
117 | #define CONFIG_SYS_PROMPT "DM365 EVM # " /* Monitor Command Prompt */ | |
118 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
119 | #define CONFIG_SYS_PBSIZE /* Print buffer size */ \ | |
120 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
121 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
122 | #define CONFIG_SYS_HUSH_PARSER | |
123 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
124 | #define CONFIG_SYS_LONGHELP | |
125 | ||
126 | #ifdef CONFIG_NAND_DAVINCI | |
a16df2c1 | 127 | #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ |
2d4072c0 SP |
128 | #define CONFIG_ENV_IS_IN_NAND |
129 | #define CONFIG_ENV_OFFSET 0x3C0000 | |
130 | #undef CONFIG_ENV_IS_IN_FLASH | |
131 | #endif | |
132 | ||
133 | #define CONFIG_BOOTDELAY 3 | |
134 | #define CONFIG_BOOTCOMMAND \ | |
135 | "dhcp;bootm" | |
136 | #define CONFIG_BOOTARGS \ | |
137 | "console=ttyS0,115200n8 " \ | |
138 | "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" | |
139 | ||
140 | #define CONFIG_CMDLINE_EDITING | |
141 | #define CONFIG_VERSION_VARIABLE | |
142 | #define CONFIG_TIMESTAMP | |
143 | ||
144 | /* U-Boot memory configuration */ | |
a16df2c1 SP |
145 | #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ |
146 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ | |
2d4072c0 SP |
147 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ |
148 | #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ | |
149 | #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ | |
150 | ||
151 | /* Linux interfacing */ | |
152 | #define CONFIG_CMDLINE_TAG | |
153 | #define CONFIG_SETUP_MEMORY_TAGS | |
154 | #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ | |
155 | #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ | |
156 | ||
157 | ||
158 | /* NAND configuration issocketed with two chipselects just like the DM355 EVM. | |
159 | * It normally comes with a 2GByte SLC part with 2KB pages | |
160 | * (and 128KB erase blocks); other | |
161 | * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC | |
162 | * pretty much demands the 4-bit ECC support.) You can of course swap in | |
163 | * other parts, including small page ones. | |
164 | */ | |
165 | #define MTDIDS_DEFAULT "nand0=davinci_nand.0" | |
166 | ||
167 | #ifdef CONFIG_SYS_NAND_LARGEPAGE | |
168 | /* Use same layout for 128K/256K blocks; allow some bad blocks */ | |
169 | #define PART_BOOT "2m(bootloader)ro," | |
170 | #else | |
171 | /* Assume 16K erase blocks; allow a few bad ones. */ | |
172 | #define PART_BOOT "512k(bootloader)ro," | |
173 | #endif | |
174 | ||
175 | #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ | |
176 | #define PART_REST "-(filesystem)" | |
177 | ||
178 | #define MTDPARTS_DEFAULT \ | |
179 | "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST | |
180 | ||
181 | #endif /* __CONFIG_H */ |