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c7f879ec HV |
1 | /* |
2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
3 | * | |
2b1fa9d3 HV |
4 | * Copyright (C) 2008 Lyrtech <www.lyrtech.com> |
5 | * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> | |
6 | * | |
c7f879ec HV |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | #include <asm/sizes.h> | |
26 | ||
c7f879ec | 27 | /* Board */ |
c7f879ec | 28 | #define SFFSDR |
6d0f6bcf JCPV |
29 | #define CONFIG_SYS_NAND_LARGEPAGE |
30 | #define CONFIG_SYS_USE_NAND | |
31 | #define CONFIG_SYS_USE_DSPLINK /* This is to prevent U-Boot from | |
2b1fa9d3 | 32 | * powering ON the DSP. */ |
c7f879ec | 33 | /* SoC Configuration */ |
c7f879ec HV |
34 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
35 | #define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ | |
6d0f6bcf JCPV |
36 | #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ |
37 | #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ | |
38 | #define CONFIG_SYS_HZ 1000 | |
2b1fa9d3 | 39 | /* EEPROM definitions for Atmel 24LC64 EEPROM chip */ |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
41 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
42 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
43 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
c7f879ec | 44 | /* Memory Info */ |
6d0f6bcf JCPV |
45 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ |
46 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ | |
47 | #define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ | |
48 | #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ | |
c7f879ec HV |
49 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
50 | #define CONFIG_STACKSIZE (256*1024) /* regular stack */ | |
51 | #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ | |
52 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ | |
53 | #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ | |
c7f879ec | 54 | /* Serial Driver info */ |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_NS16550 |
56 | #define CONFIG_SYS_NS16550_SERIAL | |
57 | #define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */ | |
58 | #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ | |
59 | #define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */ | |
c7f879ec HV |
60 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
61 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
c7f879ec | 63 | /* I2C Configuration */ |
c7f879ec HV |
64 | #define CONFIG_HARD_I2C |
65 | #define CONFIG_DRIVER_DAVINCI_I2C | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ |
67 | #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
c7f879ec | 68 | /* Network & Ethernet Configuration */ |
c7f879ec HV |
69 | #define CONFIG_DRIVER_TI_EMAC |
70 | #define CONFIG_MII | |
71 | #define CONFIG_BOOTP_DEFAULT | |
72 | #define CONFIG_BOOTP_DNS | |
73 | #define CONFIG_BOOTP_DNS2 | |
74 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
75 | #define CONFIG_NET_RETRY_COUNT 10 | |
76 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
c7f879ec | 77 | /* Flash & Environment */ |
5a1aceb0 | 78 | #undef CONFIG_ENV_IS_IN_FLASH |
6d0f6bcf | 79 | #define CONFIG_SYS_NO_FLASH |
51bfee19 | 80 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
0e8d1586 JCPV |
81 | #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ |
82 | #define CONFIG_ENV_SIZE SZ_128K | |
c7f879ec HV |
83 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
84 | #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_NAND_BASE 0x02000000 |
86 | #define CONFIG_SYS_NAND_HW_ECC | |
87 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
0e8d1586 | 88 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
2b1fa9d3 | 89 | /* I2C switch definitions for PCA9543 chip */ |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 |
91 | #define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ | |
92 | #define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ | |
c7f879ec | 93 | /* U-Boot general configuration */ |
2b1fa9d3 | 94 | #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ |
c7f879ec | 95 | #define CONFIG_MISC_INIT_R |
2b1fa9d3 | 96 | #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ |
c7f879ec | 97 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ |
99 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
100 | #define CONFIG_SYS_PBSIZE \ | |
101 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ | |
102 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
104 | #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel | |
c7f879ec HV |
105 | * load address. */ |
106 | #define CONFIG_VERSION_VARIABLE | |
107 | #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, | |
108 | * may be later */ | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_HUSH_PARSER |
110 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
c7f879ec | 111 | #define CONFIG_CMDLINE_EDITING |
6d0f6bcf | 112 | #define CONFIG_SYS_LONGHELP |
c7f879ec HV |
113 | #define CONFIG_CRC32_VERIFY |
114 | #define CONFIG_MX_CYCLIC | |
c7f879ec | 115 | /* Linux Information */ |
c7f879ec HV |
116 | #define LINUX_BOOT_PARAM_ADDR 0x80000100 |
117 | #define CONFIG_CMDLINE_TAG | |
118 | #define CONFIG_SETUP_MEMORY_TAGS | |
2b1fa9d3 HV |
119 | #define CONFIG_BOOTARGS \ |
120 | "mem=56M " \ | |
121 | "console=ttyS0,115200n8 " \ | |
122 | "root=/dev/nfs rw noinitrd ip=dhcp " \ | |
123 | "nfsroot=${serverip}:/nfsroot/sffsdr " \ | |
124 | "eth0=${ethaddr}" | |
125 | #define CONFIG_BOOTCOMMAND \ | |
126 | "nand read 87A00000 100000 300000;" \ | |
127 | "bootelf 87A00000" | |
c7f879ec | 128 | /* U-Boot commands */ |
c7f879ec HV |
129 | #include <config_cmd_default.h> |
130 | #define CONFIG_CMD_ASKENV | |
131 | #define CONFIG_CMD_DHCP | |
132 | #define CONFIG_CMD_DIAG | |
133 | #define CONFIG_CMD_I2C | |
134 | #define CONFIG_CMD_MII | |
135 | #define CONFIG_CMD_PING | |
136 | #define CONFIG_CMD_SAVES | |
137 | #define CONFIG_CMD_NAND | |
138 | #define CONFIG_CMD_EEPROM | |
c15947d6 | 139 | #define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */ |
c7f879ec HV |
140 | #undef CONFIG_CMD_BDI |
141 | #undef CONFIG_CMD_FPGA | |
142 | #undef CONFIG_CMD_SETGETDCR | |
143 | #undef CONFIG_CMD_FLASH | |
144 | #undef CONFIG_CMD_IMLS | |
c7f879ec | 145 | /* KGDB support (if any) */ |
c7f879ec HV |
146 | #ifdef CONFIG_CMD_KGDB |
147 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ | |
148 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
149 | #endif | |
150 | #endif /* __CONFIG_H */ |