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dd580801 | 1 | /* |
c4be10b5 | 2 | * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> |
dd580801 SR |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef _CONFIG_DB_MV7846MP_GP_H | |
8 | #define _CONFIG_DB_MV7846MP_GP_H | |
9 | ||
10 | /* | |
11 | * High Level Configuration Options (easy to change) | |
12 | */ | |
2554167c SR |
13 | #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ |
14 | ||
dd580801 SR |
15 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
16 | ||
2923c2d2 SR |
17 | /* |
18 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
19 | * for DDR ECC byte filling in the SPL before loading the main | |
20 | * U-Boot into it. | |
21 | */ | |
22 | #define CONFIG_SYS_TEXT_BASE 0x00800000 | |
dd580801 SR |
23 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
24 | ||
25 | /* | |
26 | * Commands configuration | |
27 | */ | |
41e705ac | 28 | #define CONFIG_CMD_PCI |
dd580801 SR |
29 | |
30 | /* I2C */ | |
31 | #define CONFIG_SYS_I2C | |
32 | #define CONFIG_SYS_I2C_MVTWSI | |
dd82242b | 33 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
dd580801 SR |
34 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
35 | #define CONFIG_SYS_I2C_SPEED 100000 | |
36 | ||
49114c87 | 37 | /* USB/EHCI configuration */ |
49114c87 | 38 | #define CONFIG_EHCI_IS_TDI |
8a333716 | 39 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
49114c87 | 40 | |
dd580801 SR |
41 | /* SPI NOR flash default params, used by sf commands */ |
42 | #define CONFIG_SF_DEFAULT_SPEED 1000000 | |
43 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
dd580801 SR |
44 | |
45 | /* Environment in SPI NOR flash */ | |
dd580801 SR |
46 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
47 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ | |
48 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ | |
49 | ||
50 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ | |
dd580801 | 51 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
dd580801 | 52 | |
dd580801 SR |
53 | #define CONFIG_SYS_ALT_MEMTEST |
54 | ||
e863f7f0 | 55 | /* SATA support */ |
c4be10b5 SR |
56 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
57 | #define CONFIG_SATA_MV | |
58 | #define CONFIG_LIBATA | |
59 | #define CONFIG_LBA48 | |
e863f7f0 | 60 | |
8c822825 SR |
61 | /* Additional FS support/configuration */ |
62 | #define CONFIG_SUPPORT_VFAT | |
63 | ||
41e705ac | 64 | /* PCIe support */ |
6451223a | 65 | #ifndef CONFIG_SPL_BUILD |
41e705ac | 66 | #define CONFIG_PCI_MVEBU |
41e705ac | 67 | #define CONFIG_PCI_SCAN_SHOW |
6451223a | 68 | #endif |
41e705ac | 69 | |
d6b6303d SR |
70 | /* NAND */ |
71 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
72 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
73 | ||
dd580801 SR |
74 | /* |
75 | * mv-common.h should be defined after CMD configs since it used them | |
76 | * to enable certain macros | |
77 | */ | |
78 | #include "mv-common.h" | |
79 | ||
2554167c SR |
80 | /* |
81 | * Memory layout while starting into the bin_hdr via the | |
82 | * BootROM: | |
83 | * | |
84 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) | |
85 | * 0x4000.4030 bin_hdr start address | |
86 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) | |
87 | * 0x4007.fffc BootROM stack top | |
88 | * | |
89 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in | |
90 | * L2 cache thus cannot be used. | |
91 | */ | |
92 | ||
93 | /* SPL */ | |
94 | /* Defines for SPL */ | |
95 | #define CONFIG_SPL_FRAMEWORK | |
96 | #define CONFIG_SPL_TEXT_BASE 0x40004030 | |
97 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) | |
98 | ||
99 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) | |
100 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
101 | ||
6451223a SR |
102 | #ifdef CONFIG_SPL_BUILD |
103 | #define CONFIG_SYS_MALLOC_SIMPLE | |
104 | #endif | |
2554167c SR |
105 | |
106 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
107 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
108 | ||
2554167c | 109 | /* SPL related SPI defines */ |
2554167c | 110 | #define CONFIG_SPL_SPI_LOAD |
2554167c | 111 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 |
2bd8711e | 112 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
2554167c SR |
113 | |
114 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ | |
2554167c | 115 | #define CONFIG_SPD_EEPROM 0x4e |
698ffab2 | 116 | #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ |
2554167c | 117 | |
dd580801 | 118 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |