[people/ms/u-boot.git] / include / configs / db-mv784mp-gp.h

/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_ARMADA_XP		/* SOC Family Name */
#define CONFIG_DB_784MP_GP		/* Board target name for DDR training */

#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_TIME
#define CONFIG_CMD_USB

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* USB/EHCI configuration */
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define CONFIG_PHY_ADDR			{ 0x10, 0x11, 0x12, 0x13 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R

#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST

/* SATA support */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE

/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO

#define CONFIG_SYS_ATA_REG_OFFSET	0x0100 /* Offset for register access */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0100 /* Offset for data I/O */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4

/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	CONFIG_SYS_IDE_MAXBUS

/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	MVEBU_AXP_SATA_BASE
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x2000
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x4000

#define CONFIG_DOS_PARTITION
#endif /* CONFIG_CMD_IDE */

/* PCIe support */
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_E1000	/* enable Intel E1000 support for testing */

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					 CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(16 << 10)

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS		0
#define CONFIG_SPL_SPI_CS		0
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_SPD_EEPROM		0x4e

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
dd580801 SR	1	/*
	2	* Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_DB_MV7846MP_GP_H
	8	#define _CONFIG_DB_MV7846MP_GP_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_ARMADA_XP /* SOC Family Name */
2554167c SR	14	#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
2554167c SR	15
dd580801 SR	16	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
	17	#define CONFIG_SYS_GENERIC_BOARD
	18	#define CONFIG_DISPLAY_BOARDINFO_LATE
	19
2923c2d2 SR	20	/*
	21	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	22	* for DDR ECC byte filling in the SPL before loading the main
	23	* U-Boot into it.
	24	*/
	25	#define CONFIG_SYS_TEXT_BASE 0x00800000
dd580801 SR	26	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	27
	28	/*
	29	* Commands configuration
	30	*/
	31	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
dd580801 SR	32	#define CONFIG_CMD_DHCP
	33	#define CONFIG_CMD_ENV
	34	#define CONFIG_CMD_I2C
e863f7f0	35	#define CONFIG_CMD_IDE
41e705ac	36	#define CONFIG_CMD_PCI
dd580801 SR	37	#define CONFIG_CMD_PING
	38	#define CONFIG_CMD_SF
	39	#define CONFIG_CMD_SPI
	40	#define CONFIG_CMD_TFTPPUT
	41	#define CONFIG_CMD_TIME
49114c87	42	#define CONFIG_CMD_USB
dd580801 SR	43
	44	/* I2C */
	45	#define CONFIG_SYS_I2C
	46	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	47	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
dd580801 SR	48	#define CONFIG_SYS_I2C_SLAVE 0x0
	49	#define CONFIG_SYS_I2C_SPEED 100000
	50
49114c87 SR	51	/* USB/EHCI configuration */
	52	#define CONFIG_USB_EHCI
	53	#define CONFIG_USB_STORAGE
	54	#define CONFIG_USB_EHCI_MARVELL
	55	#define CONFIG_EHCI_IS_TDI
8a333716	56	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
49114c87	57
dd580801 SR	58	/* SPI NOR flash default params, used by sf commands */
	59	#define CONFIG_SF_DEFAULT_SPEED 1000000
	60	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	61	#define CONFIG_SPI_FLASH_STMICRO
	62
	63	/* Environment in SPI NOR flash */
	64	#define CONFIG_ENV_IS_IN_SPI_FLASH
	65	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	66	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	67	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	68
	69	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
cae9008f	70	#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
dd580801 SR	71	#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
	72	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	73	#define CONFIG_RESET_PHY_R
	74
	75	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	76	#define CONFIG_SYS_ALT_MEMTEST
	77
e863f7f0 AS	78	/* SATA support */
	79	#ifdef CONFIG_CMD_IDE
	80	#define __io
	81	#define CONFIG_IDE_PREINIT
	82	#define CONFIG_MVSATA_IDE
	83
	84	/* Needs byte-swapping for ATA data register */
	85	#define CONFIG_IDE_SWAP_IO
	86
	87	#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
	88	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
	89	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
	90
	91	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	92	#define CONFIG_SYS_ATA_STRIDE 4
	93
	94	/* CONFIG_CMD_IDE requires some #defines for ATA registers */
	95	#define CONFIG_SYS_IDE_MAXBUS 2
	96	#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
	97
	98	/* ATA registers base is at SATA controller base */
	99	#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
	100	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
	101	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
	102
	103	#define CONFIG_DOS_PARTITION
	104	#endif /* CONFIG_CMD_IDE */
	105
41e705ac SR	106	/* PCIe support */
	107	#define CONFIG_PCI
	108	#define CONFIG_PCI_MVEBU
	109	#define CONFIG_PCI_PNP
	110	#define CONFIG_PCI_SCAN_SHOW
	111	#define CONFIG_E1000 /* enable Intel E1000 support for testing */
	112
dd580801 SR	113	/*
	114	* mv-common.h should be defined after CMD configs since it used them
	115	* to enable certain macros
	116	*/
	117	#include "mv-common.h"
	118
2554167c SR	119	/*
	120	* Memory layout while starting into the bin_hdr via the
	121	* BootROM:
	122	*
	123	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	124	* 0x4000.4030 bin_hdr start address
	125	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	126	* 0x4007.fffc BootROM stack top
	127	*
	128	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	129	* L2 cache thus cannot be used.
	130	*/
	131
	132	/* SPL */
	133	/* Defines for SPL */
	134	#define CONFIG_SPL_FRAMEWORK
	135	#define CONFIG_SPL_TEXT_BASE 0x40004030
	136	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	137
	138	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	139	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	140
	141	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	142	CONFIG_SPL_BSS_MAX_SIZE)
	143	#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
	144
	145	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	146	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	147
	148	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	149	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	150	#define CONFIG_SPL_SERIAL_SUPPORT
	151	#define CONFIG_SPL_I2C_SUPPORT
2554167c SR	152
	153	/* SPL related SPI defines */
	154	#define CONFIG_SPL_SPI_SUPPORT
	155	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	156	#define CONFIG_SPL_SPI_LOAD
	157	#define CONFIG_SPL_SPI_BUS 0
	158	#define CONFIG_SPL_SPI_CS 0
	159	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
2bd8711e	160	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
2554167c SR	161
2554167c SR	162	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
ff9112df	163	#define CONFIG_SYS_MVEBU_DDR_AXP
2554167c SR	164	#define CONFIG_SPD_EEPROM 0x4e
2554167c SR	165
dd580801	166	#endif /* _CONFIG_DB_MV7846MP_GP_H */