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disable imls command if no flash is defined
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1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the dbau1x00 board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32#define CONFIG_DBAU1X00 1
8bde63eb 33#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 34
a2663ea4 35#ifdef CONFIG_DBAU1000
5da627a4 36/* Also known as Merlot */
8bde63eb 37#define CONFIG_SOC_AU1000 1
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38#else
39#ifdef CONFIG_DBAU1100
8bde63eb 40#define CONFIG_SOC_AU1100 1
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41#else
42#ifdef CONFIG_DBAU1500
8bde63eb 43#define CONFIG_SOC_AU1500 1
d4ca31c4 44#else
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45#ifdef CONFIG_DBAU1550
46/* Cabernet */
8bde63eb 47#define CONFIG_SOC_AU1550 1
ff36fd85 48#else
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49#error "No valid board set"
50#endif
51#endif
52#endif
ff36fd85 53#endif
5da627a4 54
d4ca31c4 55#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
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56
57#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
58
59#define CONFIG_BAUDRATE 115200
60
61/* valid baudrates */
6d0f6bcf 62#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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63
64#define CONFIG_TIMESTAMP /* Print image info with timestamp */
65#undef CONFIG_BOOTARGS
66
67#define CONFIG_EXTRA_ENV_SETTINGS \
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68 "addmisc=setenv bootargs ${bootargs} " \
69 "console=ttyS0,${baudrate} " \
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70 "panic=1\0" \
71 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 72 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 73 ""
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74
75#ifdef CONFIG_DBAU1550
76/* Boot from flash by default, revert to bootp */
77#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 78#else /* CONFIG_DBAU1550 */
ad88297e 79#define CONFIG_BOOTCOMMAND "bootp;bootm"
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80#endif /* CONFIG_DBAU1550 */
81
ab999ba1 82
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83/*
84 * BOOTP options
85 */
86#define CONFIG_BOOTP_BOOTFILESIZE
87#define CONFIG_BOOTP_BOOTPATH
88#define CONFIG_BOOTP_GATEWAY
89#define CONFIG_BOOTP_HOSTNAME
90
91
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92/*
93 * Command line configuration.
94 */
95#include <config_cmd_default.h>
96
97#undef CONFIG_CMD_BDI
98#undef CONFIG_CMD_BEDBUG
99#undef CONFIG_CMD_ELF
100#undef CONFIG_CMD_ENV
101#undef CONFIG_CMD_FAT
102#undef CONFIG_CMD_FPGA
103#undef CONFIG_CMD_MII
104#undef CONFIG_CMD_RUN
105
106
107#ifdef CONFIG_DBAU1550
108
109#define CONFIG_CMD_FLASH
110#define CONFIG_CMD_LOADB
111#define CONFIG_CMD_NET
112
113#undef CONFIG_CMD_I2C
114#undef CONFIG_CMD_IDE
115#undef CONFIG_CMD_NFS
116#undef CONFIG_CMD_PCMCIA
117
118#else
119
120#define CONFIG_CMD_IDE
121#define CONFIG_CMD_DHCP
122
123#undef CONFIG_CMD_FLASH
124#undef CONFIG_CMD_LOADB
125#undef CONFIG_CMD_LOADS
126
127#endif
128
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129
130/*
131 * Miscellaneous configurable options
132 */
6d0f6bcf 133#define CONFIG_SYS_LONGHELP /* undef to save memory */
ff36fd85 134
6d0f6bcf 135#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
ff36fd85 136
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137#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
139#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
5da627a4 140
6d0f6bcf 141#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 142
6d0f6bcf 143#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 144
6d0f6bcf 145#define CONFIG_SYS_MHZ 396
ff36fd85 146
6d0f6bcf 147#if (CONFIG_SYS_MHZ % 12) != 0
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148#error "Invalid CPU frequency - must be multiple of 12!"
149#endif
150
6d0f6bcf 151#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 152
6d0f6bcf 153#define CONFIG_SYS_HZ 1000
5da627a4 154
6d0f6bcf 155#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 156
6d0f6bcf 157#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 158
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159#define CONFIG_SYS_MEMTEST_START 0x80100000
160#define CONFIG_SYS_MEMTEST_END 0x80800000
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161
162/*-----------------------------------------------------------------------
163 * FLASH and environment organization
164 */
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165#ifdef CONFIG_DBAU1550
166
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167#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
168#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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169
170#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
171#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
172
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173#else /* CONFIG_DBAU1550 */
174
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175#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
176#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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177
178#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
179#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
180
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181#endif /* CONFIG_DBAU1550 */
182
6d0f6bcf 183#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 184
6d0f6bcf 185#define CONFIG_SYS_FLASH_CFI 1
00b1883a 186#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 187
5da627a4 188/* The following #defines are needed to get flash environment right */
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189#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
190#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 191
6d0f6bcf 192#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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193
194/* We boot from this flash, selected with dip switch */
6d0f6bcf 195#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
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196
197/* timeout values are in ticks */
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198#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
199#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 200
93f6d725 201#define CONFIG_ENV_IS_NOWHERE 1
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202
203/* Address and size of Primary Environment Sector */
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204#define CONFIG_ENV_ADDR 0xB0030000
205#define CONFIG_ENV_SIZE 0x10000
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206
207#define CONFIG_FLASH_16BIT
208
209#define CONFIG_NR_DRAM_BANKS 2
210
211#define CONFIG_NET_MULTI
212
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213#ifdef CONFIG_DBAU1550
214#define MEM_SIZE 192
215#else
216#define MEM_SIZE 64
217#endif
218
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219#define CONFIG_MEMSIZE_IN_BYTES
220
ff36fd85 221#ifndef CONFIG_DBAU1550
5da627a4 222/*---ATA PCMCIA ------------------------------------*/
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223#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
224#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
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225#define CONFIG_PCMCIA_SLOT_A
226
227#define CONFIG_ATAPI 1
228#define CONFIG_MAC_PARTITION 1
229
230/* We run CF in "true ide" mode or a harddrive via pcmcia */
231#define CONFIG_IDE_PCMCIA 1
232
233/* We only support one slot for now */
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234#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
235#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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236
237#undef CONFIG_IDE_LED /* LED for ide not supported */
238#undef CONFIG_IDE_RESET /* reset for ide not supported */
239
6d0f6bcf 240#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 241
6d0f6bcf 242#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 243
d4ca31c4 244/* Offset for data I/O */
6d0f6bcf 245#define CONFIG_SYS_ATA_DATA_OFFSET 8
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246
247/* Offset for normal register accesses */
6d0f6bcf 248#define CONFIG_SYS_ATA_REG_OFFSET 0
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249
250/* Offset for alternate registers */
6d0f6bcf 251#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 252#endif /* CONFIG_DBAU1550 */
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253
254/*-----------------------------------------------------------------------
255 * Cache Configuration
256 */
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257#define CONFIG_SYS_DCACHE_SIZE 16384
258#define CONFIG_SYS_ICACHE_SIZE 16384
259#define CONFIG_SYS_CACHELINE_SIZE 32
5da627a4 260
5da627a4 261#endif /* __CONFIG_H */