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1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
5da627a4 15#define CONFIG_DBAU1X00 1
8bde63eb 16#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 17
a2663ea4 18#ifdef CONFIG_DBAU1000
5da627a4 19/* Also known as Merlot */
8bde63eb 20#define CONFIG_SOC_AU1000 1
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21#else
22#ifdef CONFIG_DBAU1100
8bde63eb 23#define CONFIG_SOC_AU1100 1
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24#else
25#ifdef CONFIG_DBAU1500
8bde63eb 26#define CONFIG_SOC_AU1500 1
d4ca31c4 27#else
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28#ifdef CONFIG_DBAU1550
29/* Cabernet */
8bde63eb 30#define CONFIG_SOC_AU1550 1
ff36fd85 31#else
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32#error "No valid board set"
33#endif
34#endif
35#endif
ff36fd85 36#endif
5da627a4 37
5da627a4 38/* valid baudrates */
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39
40#define CONFIG_TIMESTAMP /* Print image info with timestamp */
41#undef CONFIG_BOOTARGS
42
43#define CONFIG_EXTRA_ENV_SETTINGS \
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44 "addmisc=setenv bootargs ${bootargs} " \
45 "console=ttyS0,${baudrate} " \
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46 "panic=1\0" \
47 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 48 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 49 ""
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50
51#ifdef CONFIG_DBAU1550
52/* Boot from flash by default, revert to bootp */
53#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 54#else /* CONFIG_DBAU1550 */
ad88297e 55#define CONFIG_BOOTCOMMAND "bootp;bootm"
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56#endif /* CONFIG_DBAU1550 */
57
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58/*
59 * BOOTP options
60 */
61#define CONFIG_BOOTP_BOOTFILESIZE
62#define CONFIG_BOOTP_BOOTPATH
63#define CONFIG_BOOTP_GATEWAY
64#define CONFIG_BOOTP_HOSTNAME
65
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66/*
67 * Command line configuration.
68 */
ab999ba1 69#undef CONFIG_CMD_BEDBUG
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70
71#ifdef CONFIG_DBAU1550
72
ab999ba1 73#undef CONFIG_CMD_IDE
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74#undef CONFIG_CMD_PCMCIA
75
76#else
77
78#define CONFIG_CMD_IDE
ab999ba1 79
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80#endif
81
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82/*
83 * Miscellaneous configurable options
84 */
6d0f6bcf 85#define CONFIG_SYS_LONGHELP /* undef to save memory */
ff36fd85 86
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87#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
88#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
89#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
5da627a4 90
6d0f6bcf 91#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 92
6d0f6bcf 93#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 94
6d0f6bcf 95#define CONFIG_SYS_MHZ 396
ff36fd85 96
6d0f6bcf 97#if (CONFIG_SYS_MHZ % 12) != 0
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98#error "Invalid CPU frequency - must be multiple of 12!"
99#endif
100
6d0f6bcf 101#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 102
6d0f6bcf 103#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 104
6d0f6bcf 105#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 106
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107#define CONFIG_SYS_MEMTEST_START 0x80100000
108#define CONFIG_SYS_MEMTEST_END 0x80800000
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109
110/*-----------------------------------------------------------------------
111 * FLASH and environment organization
112 */
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113#ifdef CONFIG_DBAU1550
114
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115#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
116#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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117
118#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
119#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
120
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121#else /* CONFIG_DBAU1550 */
122
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123#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
124#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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125
126#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
127#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
128
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129#endif /* CONFIG_DBAU1550 */
130
6d0f6bcf 131#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 132
6d0f6bcf 133#define CONFIG_SYS_FLASH_CFI 1
00b1883a 134#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 135
14d0a02a 136#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 137#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 138
6d0f6bcf 139#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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140
141/* We boot from this flash, selected with dip switch */
6d0f6bcf 142#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
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143
144/* timeout values are in ticks */
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145#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
146#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 147
93f6d725 148#define CONFIG_ENV_IS_NOWHERE 1
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149
150/* Address and size of Primary Environment Sector */
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151#define CONFIG_ENV_ADDR 0xB0030000
152#define CONFIG_ENV_SIZE 0x10000
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153
154#define CONFIG_FLASH_16BIT
155
156#define CONFIG_NR_DRAM_BANKS 2
157
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158#ifdef CONFIG_DBAU1550
159#define MEM_SIZE 192
160#else
161#define MEM_SIZE 64
162#endif
163
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164#define CONFIG_MEMSIZE_IN_BYTES
165
ff36fd85 166#ifndef CONFIG_DBAU1550
5da627a4 167/*---ATA PCMCIA ------------------------------------*/
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168#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
169#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
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170#define CONFIG_PCMCIA_SLOT_A
171
172#define CONFIG_ATAPI 1
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173
174/* We run CF in "true ide" mode or a harddrive via pcmcia */
175#define CONFIG_IDE_PCMCIA 1
176
177/* We only support one slot for now */
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178#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
179#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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180
181#undef CONFIG_IDE_LED /* LED for ide not supported */
182#undef CONFIG_IDE_RESET /* reset for ide not supported */
183
6d0f6bcf 184#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 185
6d0f6bcf 186#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 187
d4ca31c4 188/* Offset for data I/O */
6d0f6bcf 189#define CONFIG_SYS_ATA_DATA_OFFSET 8
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190
191/* Offset for normal register accesses */
6d0f6bcf 192#define CONFIG_SYS_ATA_REG_OFFSET 0
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193
194/* Offset for alternate registers */
6d0f6bcf 195#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 196#endif /* CONFIG_DBAU1550 */
5da627a4 197
5da627a4 198#endif /* __CONFIG_H */