[people/ms/u-boot.git] / include / configs / devkit3250.h

/*
 * Embest/Timll DevKit3250 board configuration file
 *
 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_DEVKIT3250_H__
#define __CONFIG_DEVKIT3250_H__

/* SoC and board defines */
#include <linux/sizes.h>
#include <asm/arch/cpu.h>

/*
 * Define DevKit3250 machine type by hand until it lands in mach-types
 */
#define MACH_TYPE_DEVKIT3250		3697
#define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250

#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_BOARD_EARLY_INIT_F

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_MALLOC_LEN		SZ_1M
#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
#define CONFIG_SYS_TEXT_BASE		0x83FA0000
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
					 - GENERATED_GBL_DATA_SIZE)

/*
 * Serial Driver
 */
#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 */
#define CONFIG_BAUDRATE			115200

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_LPC32XX
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_CMD_I2C

/*
 * GPIO
 */
#define CONFIG_LPC32XX_GPIO
#define CONFIG_CMD_GPIO

/*
 * SSP/SPI
 */
#define CONFIG_LPC32XX_SSP
#define CONFIG_LPC32XX_SSP_TIMEOUT	100000
#define CONFIG_CMD_SPI

/*
 * Ethernet
 */
#define CONFIG_RMII
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR			0x1F
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP

/*
 * NOR Flash
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71
#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
#define CONFIG_SYS_FLASH_SIZE		SZ_4M
#define CONFIG_SYS_FLASH_CFI

/*
 * NAND controller
 */
#define CONFIG_NAND_LPC32XX_SLC
#define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }

/*
 * NAND chip timings
 */
#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS	14
#define CONFIG_LPC32XX_NAND_SLC_WWIDTH		66666666
#define CONFIG_LPC32XX_NAND_SLC_WHOLD		200000000
#define CONFIG_LPC32XX_NAND_SLC_WSETUP		50000000
#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS	14
#define CONFIG_LPC32XX_NAND_SLC_RWIDTH		66666666
#define CONFIG_LPC32XX_NAND_SLC_RHOLD		200000000
#define CONFIG_LPC32XX_NAND_SLC_RSETUP		50000000

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_CMD_NAND

/*
 * U-Boot General Configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_SIZE			SZ_128K
#define CONFIG_ENV_OFFSET		0x000A0000

#define CONFIG_BOOTCOMMAND			\
	"dhcp; "				\
	"tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "		\
	"tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "	\
	"setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "	\
	"setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "			\
	"bootm ${loadaddr} - ${dtbaddr}"

#define CONFIG_EXTRA_ENV_SETTINGS		\
	"autoload=no\0"				\
	"ethaddr=00:01:90:00:C0:81\0"		\
	"dtbaddr=0x81000000\0"			\
	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"	\
	"tftpdir=vladimir/oe/devkit3250\0"	\
	"userargs=oops=panic\0"

/*
 * U-Boot Commands
 */
#define CONFIG_CMD_CACHE

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTDELAY		1

#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
#define CONFIG_LOADADDR			0x80008000

/*
 * SPL specific defines
 */
/* SPL will be executed at offset 0 */
#define CONFIG_SPL_TEXT_BASE		0x00000000

/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK		0x0000FFF8
#define CONFIG_SPL_BOARD_INIT

/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT

/* SPL will use serial */
#define CONFIG_SPL_SERIAL_SUPPORT

/* SPL loads an image from NAND */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_RAW_ONLY
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_DRIVERS

#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_ECCSIZE		0x100
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
					  48, 49, 50, 51, 52, 53, 54, 55, \
					  56, 57, 58, 59, 60, 61, 62, 63, }
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS

#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SOFTECC

#define CONFIG_SPL_MAX_SIZE		0x20000
#define CONFIG_SPL_PAD_TO		CONFIG_SPL_MAX_SIZE

/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE

/* See common/spl/spl.c  spl_set_header_raw_uboot() */
#define CONFIG_SYS_MONITOR_LEN		CONFIG_SYS_NAND_U_BOOT_SIZE

/*
 * Include SoC specific configuration
 */
#include <asm/arch/config.h>

#endif  /* __CONFIG_DEVKIT3250_H__*/
Commit	Line	Data
463ec1ca VZ	1	/*
	2	* Embest/Timll DevKit3250 board configuration file
	3	*
768ddeee	4	* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
463ec1ca	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
463ec1ca VZ	7	*/
	8
	9	#ifndef __CONFIG_DEVKIT3250_H__
	10	#define __CONFIG_DEVKIT3250_H__
	11
	12	/* SoC and board defines */
1ace4022	13	#include <linux/sizes.h>
463ec1ca VZ	14	#include <asm/arch/cpu.h>
	15
	16	/*
	17	* Define DevKit3250 machine type by hand until it lands in mach-types
	18	*/
	19	#define MACH_TYPE_DEVKIT3250 3697
	20	#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
	21
	22	#define CONFIG_SYS_ICACHE_OFF
	23	#define CONFIG_SYS_DCACHE_OFF
e9b3ce3f	24	#if !defined(CONFIG_SPL_BUILD)
463ec1ca	25	#define CONFIG_SKIP_LOWLEVEL_INIT
e9b3ce3f	26	#endif
463ec1ca VZ	27	#define CONFIG_BOARD_EARLY_INIT_F
	28
	29	/*
	30	* Memory configurations
	31	*/
	32	#define CONFIG_NR_DRAM_BANKS 1
463ec1ca	33	#define CONFIG_SYS_MALLOC_LEN SZ_1M
463ec1ca VZ	34	#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
	35	#define CONFIG_SYS_SDRAM_SIZE SZ_64M
	36	#define CONFIG_SYS_TEXT_BASE 0x83FA0000
	37	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
	38	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
	39
	40	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
	41
	42	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
	43	- GENERATED_GBL_DATA_SIZE)
	44
	45	/*
	46	* Serial Driver
	47	*/
768ddeee	48	#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
463ec1ca VZ	49	#define CONFIG_BAUDRATE 115200
463ec1ca VZ	50
768ddeee VZ	51	/*
	52	* I2C
	53	*/
	54	#define CONFIG_SYS_I2C
	55	#define CONFIG_SYS_I2C_LPC32XX
	56	#define CONFIG_SYS_I2C_SPEED 100000
	57	#define CONFIG_CMD_I2C
	58
	59	/*
	60	* GPIO
	61	*/
	62	#define CONFIG_LPC32XX_GPIO
	63	#define CONFIG_CMD_GPIO
	64
	65	/*
	66	* SSP/SPI
	67	*/
	68	#define CONFIG_LPC32XX_SSP
	69	#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
	70	#define CONFIG_CMD_SPI
	71
	72	/*
	73	* Ethernet
	74	*/
	75	#define CONFIG_RMII
	76	#define CONFIG_PHY_SMSC
	77	#define CONFIG_LPC32XX_ETH
	78	#define CONFIG_PHYLIB
	79	#define CONFIG_PHY_ADDR 0x1F
	80	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	81	#define CONFIG_CMD_MII
	82	#define CONFIG_CMD_PING
	83	#define CONFIG_CMD_DHCP
	84
463ec1ca VZ	85	/*
	86	* NOR Flash
	87	*/
463ec1ca VZ	88	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	89	#define CONFIG_SYS_MAX_FLASH_SECT 71
	90	#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
	91	#define CONFIG_SYS_FLASH_SIZE SZ_4M
	92	#define CONFIG_SYS_FLASH_CFI
	93
768ddeee VZ	94	/*
	95	* NAND controller
	96	*/
	97	#define CONFIG_NAND_LPC32XX_SLC
	98	#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
	99	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	100	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	101
	102	/*
	103	* NAND chip timings
	104	*/
	105	#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
	106	#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
	107	#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
	108	#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
	109	#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
	110	#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
	111	#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
	112	#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
	113
	114	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	115	#define CONFIG_CMD_NAND
	116
463ec1ca VZ	117	/*
	118	* U-Boot General Configurations
	119	*/
	120	#define CONFIG_SYS_LONGHELP
463ec1ca VZ	121	#define CONFIG_SYS_CBSIZE 1024
	122	#define CONFIG_SYS_PBSIZE \
	123	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	124	#define CONFIG_SYS_MAXARGS 16
	125	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	126
	127	#define CONFIG_AUTO_COMPLETE
	128	#define CONFIG_CMDLINE_EDITING
	129	#define CONFIG_VERSION_VARIABLE
	130	#define CONFIG_DISPLAY_CPUINFO
	131	#define CONFIG_DOS_PARTITION
	132
768ddeee VZ	133	/*
	134	* Pass open firmware flat tree
	135	*/
	136	#define CONFIG_OF_LIBFDT
	137
	138	/*
	139	* Environment
	140	*/
	141	#define CONFIG_ENV_IS_IN_NAND 1
463ec1ca	142	#define CONFIG_ENV_SIZE SZ_128K
768ddeee VZ	143	#define CONFIG_ENV_OFFSET 0x000A0000
	144
	145	#define CONFIG_BOOTCOMMAND \
	146	"dhcp; " \
	147	"tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
	148	"tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
	149	"setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
	150	"setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
	151	"bootm ${loadaddr} - ${dtbaddr}"
	152
	153	#define CONFIG_EXTRA_ENV_SETTINGS \
	154	"autoload=no\0" \
	155	"ethaddr=00:01:90:00:C0:81\0" \
	156	"dtbaddr=0x81000000\0" \
	157	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
	158	"tftpdir=vladimir/oe/devkit3250\0" \
	159	"userargs=oops=panic\0"
463ec1ca VZ	160
	161	/*
	162	* U-Boot Commands
	163	*/
463ec1ca VZ	164	#define CONFIG_CMD_CACHE
	165
	166	/*
	167	* Boot Linux
	168	*/
	169	#define CONFIG_CMDLINE_TAG
	170	#define CONFIG_SETUP_MEMORY_TAGS
	171	#define CONFIG_ZERO_BOOTDELAY_CHECK
768ddeee	172	#define CONFIG_BOOTDELAY 1
463ec1ca VZ	173
463ec1ca VZ	174	#define CONFIG_BOOTFILE "uImage"
768ddeee	175	#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
463ec1ca VZ	176	#define CONFIG_LOADADDR 0x80008000
463ec1ca VZ	177
e9b3ce3f VZ	178	/*
	179	* SPL specific defines
	180	*/
	181	/* SPL will be executed at offset 0 */
	182	#define CONFIG_SPL_TEXT_BASE 0x00000000
	183
	184	/* SPL will use SRAM as stack */
	185	#define CONFIG_SPL_STACK 0x0000FFF8
	186	#define CONFIG_SPL_BOARD_INIT
	187
	188	/* Use the framework and generic lib */
	189	#define CONFIG_SPL_FRAMEWORK
	190	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	191	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	192
	193	/* SPL will use serial */
	194	#define CONFIG_SPL_SERIAL_SUPPORT
	195
	196	/* SPL loads an image from NAND */
	197	#define CONFIG_SPL_NAND_SIMPLE
	198	#define CONFIG_SPL_NAND_RAW_ONLY
	199	#define CONFIG_SPL_NAND_SUPPORT
	200	#define CONFIG_SPL_NAND_DRIVERS
	201
	202	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	203	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	204	#define CONFIG_SYS_NAND_ECCSIZE 0x100
	205	#define CONFIG_SYS_NAND_OOBSIZE 64
	206	#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
	207	48, 49, 50, 51, 52, 53, 54, 55, \
	208	56, 57, 58, 59, 60, 61, 62, 63, }
	209	#define CONFIG_SYS_NAND_ECCBYTES 3
	210	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	211	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	212
	213	#define CONFIG_SPL_NAND_ECC
	214	#define CONFIG_SPL_NAND_SOFTECC
	215
	216	#define CONFIG_SPL_MAX_SIZE 0x20000
	217	#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
	218
	219	/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
	220	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	221	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
	222
	223	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	224	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	225
	226	/* See common/spl/spl.c spl_set_header_raw_uboot() */
	227	#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
	228
463ec1ca VZ	229	/*
	230	* Include SoC specific configuration
	231	*/
	232	#include <asm/arch/config.h>
	233
	234	#endif /* __CONFIG_DEVKIT3250_H__*/