[people/ms/u-boot.git] / include / configs / devkit8000.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2009
 * Frederik Kriewitz <frederik@kriewitz.eu>
 *
 * Configuration settings for the DevKit8000 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
#define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000
/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE	0x80100000

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK				26000000	/* Clock output from T2 */
#define V_SCLK				(V_OSCK >> 1)

#undef CONFIG_USE_IRQ			/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/* Size of malloc() pool */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/* Hardware drivers */
/* DM9000 */
#define CONFIG_NET_RETRY_COUNT		20
#define	CONFIG_DRIVER_DM9000		1
#define	CONFIG_DM9000_BASE		0x2c000000
#define	DM9000_IO			CONFIG_DM9000_BASE
#define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
#define	CONFIG_DM9000_USE_16BIT		1
#define CONFIG_DM9000_NO_SROM		1
#undef	CONFIG_DM9000_DEBUG

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* MMC */
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* I2C */
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/* TWL4030 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/* Board NAND Info */
#define CONFIG_SYS_NO_FLASH		/* no NOR flash */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
						"512k(x-loader)," \
						"1920k(u-boot)," \
						"128k(u-boot-env)," \
						"4m(kernel)," \
						"-(fs)"

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP			/* DHCP support			*/
#define CONFIG_CMD_EXT2			/* EXT2 Support			*/
#define CONFIG_CMD_FAT			/* FAT support			*/
#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
#define CONFIG_CMD_JFFS2		/* JFFS2 Support		*/
#define CONFIG_CMD_MMC			/* MMC support			*/
#define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands	*/
#define CONFIG_CMD_NAND			/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/

#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI			/* iminfo			*/

/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET
#undef CONFIG_BOOTP_VENDOREX

/* Environment information */
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */

#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	"kernelopts=rw\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay}\0" \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"${kernelopts}\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=/dev/mtdblock4 " \
		"rootfstype=jffs2 " \
		"${kernelopts}\0" \
	"netargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/nfs " \
		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
		"${kernelopts} " \
		"dnsip1=${dnsip} " \
		"dnsip2=${dnsip2}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"netboot=echo Booting from network ...; " \
		"dhcp ${loadaddr}; " \
		"run netargs; " \
		"bootm ${loadaddr}\0" \
	"autoboot=if mmc rescan ${mmcdev}; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"


#define CONFIG_BOOTCOMMAND "run autoboot"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_AUTO_COMPLETE		1
#define CONFIG_SYS_PROMPT		"OMAP3 DevKit8000 # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		128	/* max number of command args */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					0x01000000) /* 16MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/* The stack sizes are set up in start.S using the settings below */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */

/*  Physical Memory Map  */
#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* NAND and environment organization  */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE        0x800
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
		                                         CONFIG_SYS_INIT_RAM_SIZE - \
		                                         GENERATED_GBL_DATA_SIZE)

/* SRAM config */
#define CONFIG_SYS_SRAM_START              0x40200000
#define CONFIG_SYS_SRAM_SIZE               0x10000

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3

#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

/* SPL OS boot options */
#define CONFIG_SPL_OS_BOOT
#define CONFIG_SPL_OS_BOOT_KEY	26

#define CONFIG_CMD_SPL
#define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
					0x400000)
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)

#endif /* __CONFIG_H */
Commit	Line	Data
c35d7cf0 FK	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* (C) Copyright 2009
	8	* Frederik Kriewitz <frederik@kriewitz.eu>
	9	*
	10	* Configuration settings for the DevKit8000 board.
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
c35d7cf0 FK	33
c35d7cf0 FK	34	/* High Level Configuration Options */
c35d7cf0 FK	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
c35d7cf0 FK	36	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
c35d7cf0	37	#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
2d52a9a3	38	#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
5183b7ec SS	39	/*
	40	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	41	* 64 bytes before this address should be set aside for u-boot.img's
	42	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	43	* other needs.
	44	*/
	45	#define CONFIG_SYS_TEXT_BASE 0x80100000
66fca016	46
cae377b5 VH	47	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	48
c35d7cf0 FK	49	#include <asm/arch/cpu.h> /* get chip and board defs */
	50	#include <asm/arch/omap3.h>
	51
	52	/* Display CPU and Board information */
	53	#define CONFIG_DISPLAY_CPUINFO 1
	54	#define CONFIG_DISPLAY_BOARDINFO 1
	55
	56	/* Clock Defines */
	57	#define V_OSCK 26000000 /* Clock output from T2 */
	58	#define V_SCLK (V_OSCK >> 1)
	59
	60	#undef CONFIG_USE_IRQ /* no support for IRQs */
	61	#define CONFIG_MISC_INIT_R
	62
	63	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	64	#define CONFIG_SETUP_MEMORY_TAGS 1
	65	#define CONFIG_INITRD_TAG 1
	66	#define CONFIG_REVISION_TAG 1
	67
2fa8ca98 GL	68	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	69
c35d7cf0	70	/* Size of malloc() pool */
9c44ddcc	71	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
c35d7cf0	72	/* Sector */
9c44ddcc	73	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
c35d7cf0 FK	74
c35d7cf0 FK	75	/* Hardware drivers */
c35d7cf0	76	/* DM9000 */
c35d7cf0 FK	77	#define CONFIG_NET_RETRY_COUNT 20
	78	#define CONFIG_DRIVER_DM9000 1
	79	#define CONFIG_DM9000_BASE 0x2c000000
	80	#define DM9000_IO CONFIG_DM9000_BASE
	81	#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
	82	#define CONFIG_DM9000_USE_16BIT 1
	83	#define CONFIG_DM9000_NO_SROM 1
	84	#undef CONFIG_DM9000_DEBUG
	85
	86	/* NS16550 Configuration */
	87	#define CONFIG_SYS_NS16550
	88	#define CONFIG_SYS_NS16550_SERIAL
	89	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	90	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	91
	92	/* select serial console configuration */
	93	#define CONFIG_CONS_INDEX 3
	94	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	95	#define CONFIG_SERIAL3 3
	96	#define CONFIG_BAUDRATE 115200
	97	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	98	115200}
	99
	100	/* MMC */
f408501d	101	#define CONFIG_GENERIC_MMC 1
c35d7cf0	102	#define CONFIG_MMC 1
f408501d	103	#define CONFIG_OMAP_HSMMC 1
c35d7cf0 FK	104	#define CONFIG_DOS_PARTITION 1
	105
	106	/* I2C */
0297ec7e	107	#define CONFIG_HARD_I2C 1
c35d7cf0 FK	108	#define CONFIG_SYS_I2C_SPEED 100000
	109	#define CONFIG_SYS_I2C_SLAVE 1
	110	#define CONFIG_SYS_I2C_BUS 0
	111	#define CONFIG_SYS_I2C_BUS_SELECT 1
	112	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	113
	114	/* TWL4030 */
	115	#define CONFIG_TWL4030_POWER 1
	116	#define CONFIG_TWL4030_LED 1
	117
	118	/* Board NAND Info */
	119	#define CONFIG_SYS_NO_FLASH /* no NOR flash */
	120	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	121	#define MTDIDS_DEFAULT "nand0=nand"
	122	#define MTDPARTS_DEFAULT "mtdparts=nand:" \
	123	"512k(x-loader)," \
	124	"1920k(u-boot)," \
	125	"128k(u-boot-env)," \
	126	"4m(kernel)," \
	127	"-(fs)"
	128
	129	#define CONFIG_NAND_OMAP_GPMC
	130	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	131	/* to access nand */
	132	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	133	/* to access nand at */
	134	/* CS0 */
	135	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	136
	137	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	138	/* devices */
c35d7cf0 FK	139	#define CONFIG_JFFS2_NAND
	140	/* nand device jffs2 lives on */
	141	#define CONFIG_JFFS2_DEV "nand0"
	142	/* start of jffs2 partition */
	143	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	144	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	145	/* partition */
	146
	147	/* commands to include */
	148	#include <config_cmd_default.h>
	149
	150	#define CONFIG_CMD_DHCP /* DHCP support */
	151	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	152	#define CONFIG_CMD_FAT /* FAT support */
	153	#define CONFIG_CMD_I2C /* I2C serial bus support */
	154	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	155	#define CONFIG_CMD_MMC /* MMC support */
	156	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	157	#define CONFIG_CMD_NAND /* NAND support */
	158	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
	159
	160	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	161	#undef CONFIG_CMD_IMI /* iminfo */
	162
	163	/* BOOTP/DHCP options */
	164	#define CONFIG_BOOTP_SUBNETMASK
	165	#define CONFIG_BOOTP_GATEWAY
	166	#define CONFIG_BOOTP_HOSTNAME
	167	#define CONFIG_BOOTP_NISDOMAIN
	168	#define CONFIG_BOOTP_BOOTPATH
	169	#define CONFIG_BOOTP_BOOTFILESIZE
	170	#define CONFIG_BOOTP_DNS
	171	#define CONFIG_BOOTP_DNS2
	172	#define CONFIG_BOOTP_SEND_HOSTNAME
	173	#define CONFIG_BOOTP_NTPSERVER
	174	#define CONFIG_BOOTP_TIMEOFFSET
	175	#undef CONFIG_BOOTP_VENDOREX
	176
	177	/* Environment information */
	178	#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
	179
	180	#define CONFIG_BOOTDELAY 3
	181
	182	#define CONFIG_EXTRA_ENV_SETTINGS \
	183	"loadaddr=0x82000000\0" \
2d76da24	184	"console=ttyO2,115200n8\0" \
f408501d	185	"mmcdev=0\0" \
c35d7cf0 FK	186	"vram=12M\0" \
	187	"dvimode=1024x768MR-16@60\0" \
	188	"defaultdisplay=dvi\0" \
	189	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
	190	"kernelopts=rw\0" \
	191	"commonargs=" \
	192	"setenv bootargs console=${console} " \
	193	"vram=${vram} " \
	194	"omapfb.mode=dvi:${dvimode} " \
	195	"omapdss.def_disp=${defaultdisplay}\0" \
	196	"mmcargs=" \
	197	"run commonargs; " \
	198	"setenv bootargs ${bootargs} " \
	199	"root=/dev/mmcblk0p2 " \
	200	"${kernelopts}\0" \
	201	"nandargs=" \
	202	"run commonargs; " \
	203	"setenv bootargs ${bootargs} " \
	204	"omapfb.mode=dvi:${dvimode} " \
	205	"omapdss.def_disp=${defaultdisplay} " \
	206	"root=/dev/mtdblock4 " \
	207	"rootfstype=jffs2 " \
	208	"${kernelopts}\0" \
	209	"netargs=" \
	210	"run commonargs; " \
	211	"setenv bootargs ${bootargs} " \
	212	"root=/dev/nfs " \
	213	"nfsroot=${serverip}:${rootpath},${nfsopts} " \
	214	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
	215	"${kernelopts} " \
	216	"dnsip1=${dnsip} " \
	217	"dnsip2=${dnsip2}\0" \
f408501d	218	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
c35d7cf0 FK	219	"bootscript=echo Running bootscript from mmc ...; " \
c35d7cf0 FK	220	"source ${loadaddr}\0" \
f408501d	221	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
c35d7cf0 FK	222	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	223	"mmcboot=echo Booting from mmc ...; " \
	224	"run mmcargs; " \
	225	"bootm ${loadaddr}\0" \
	226	"nandboot=echo Booting from nand ...; " \
	227	"run nandargs; " \
	228	"nand read ${loadaddr} 280000 400000; " \
	229	"bootm ${loadaddr}\0" \
	230	"netboot=echo Booting from network ...; " \
	231	"dhcp ${loadaddr}; " \
	232	"run netargs; " \
	233	"bootm ${loadaddr}\0" \
f408501d	234	"autoboot=if mmc rescan ${mmcdev}; then " \
c35d7cf0 FK	235	"if run loadbootscript; then " \
	236	"run bootscript; " \
	237	"else " \
	238	"if run loaduimage; then " \
	239	"run mmcboot; " \
	240	"else run nandboot; " \
	241	"fi; " \
	242	"fi; " \
	243	"else run nandboot; fi\0"
	244
	245
	246	#define CONFIG_BOOTCOMMAND "run autoboot"
	247
	248	/* Miscellaneous configurable options */
	249	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	250	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	251	#define CONFIG_AUTO_COMPLETE 1
c35d7cf0 FK	252	#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
	253	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	254	/* Print Buffer Size */
	255	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	256	sizeof(CONFIG_SYS_PROMPT) + 16)
	257	#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
	258
	259	/* Boot Argument Buffer Size */
	260	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	261
	262	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
	263	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	264	0x01000000) /* 16MB */
	265
	266	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	267
	268	/*
	269	* OMAP3 has 12 GP timers, they can be driven by the system clock
	270	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	271	* This rate is divided by a local divisor.
	272	*/
	273	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	274	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	275	#define CONFIG_SYS_HZ 1000
	276
	277	/* The stack sizes are set up in start.S using the settings below */
9c44ddcc	278	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
c35d7cf0 FK	279
	280	/* Physical Memory Map */
	281	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	282	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
c35d7cf0 FK	283	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
c35d7cf0 FK	284
c35d7cf0 FK	285	/* NAND and environment organization */
	286	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	287
9c44ddcc	288	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
c35d7cf0 FK	289
	290	#define CONFIG_ENV_IS_IN_NAND 1
	291	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	292
6cbec7b3	293	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
c35d7cf0	294
66fca016	295	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
30f305c9 TW	296	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	297	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	298	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	299	CONFIG_SYS_INIT_RAM_SIZE - \
	300	GENERATED_GBL_DATA_SIZE)
66fca016	301
3f6a4922 SS	302	/* SRAM config */
	303	#define CONFIG_SYS_SRAM_START 0x40200000
	304	#define CONFIG_SYS_SRAM_SIZE 0x10000
	305
	306	/* Defines for SPL */
	307	#define CONFIG_SPL
	308	#define CONFIG_SPL_NAND_SIMPLE
	309
	310	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	311	#define CONFIG_SPL_LIBDISK_SUPPORT
ee08a826	312	#define CONFIG_SPL_BOARD_INIT
3f6a4922 SS	313	#define CONFIG_SPL_I2C_SUPPORT
	314	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	315	#define CONFIG_SPL_SERIAL_SUPPORT
16e41c85	316	#define CONFIG_SPL_GPIO_SUPPORT
3f6a4922 SS	317	#define CONFIG_SPL_POWER_SUPPORT
3f6a4922 SS	318	#define CONFIG_SPL_NAND_SUPPORT
99154714 SS	319	#define CONFIG_SPL_MMC_SUPPORT
99154714 SS	320	#define CONFIG_SPL_FAT_SUPPORT
3f6a4922	321	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
99154714 SS	322	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	323	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	324	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
3f6a4922 SS	325
3f6a4922 SS	326	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	327	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
3f6a4922 SS	328	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
3f6a4922 SS	329
2d52a9a3	330	#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
3f6a4922 SS	331	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	332
	333	/* NAND boot config */
c471ccb9	334	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
3f6a4922 SS	335	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	336	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	337	#define CONFIG_SYS_NAND_OOBSIZE 64
	338	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	339	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	340	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	341	10, 11, 12, 13}
	342
	343	#define CONFIG_SYS_NAND_ECCSIZE 512
	344	#define CONFIG_SYS_NAND_ECCBYTES 3
	345
3f6a4922 SS	346	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	347
	348	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	349	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
	350
5183b7ec	351	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
ba75a81a TR	352	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
ba75a81a TR	353
d38bc97d	354	/* SPL OS boot options */
2d52a9a3 SS	355	#define CONFIG_SPL_OS_BOOT
	356	#define CONFIG_SPL_OS_BOOT_KEY 26
	357
d38bc97d SS	358	#define CONFIG_CMD_SPL
	359	#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
	360	#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
	361	0x400000)
	362	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
	363	#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
	364
c35d7cf0	365	#endif /* __CONFIG_H */