projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c4fa9b4 GB |
1 | /* |
| 2 | * (C) Copyright 2003-2004 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * (C) Copyright 2005-2007 | |
| 6 | * Modified for InterControl digsyMTC MPC5200 board by | |
| 7 | * Frank Bodammer, GCD Hard- & Software GmbH, | |
| 8 | * frank.bodammer@gcd-solutions.de | |
| 9 | * | |
| 10 | * (C) Copyright 2009 Semihalf | |
| 11 | * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com> | |
| 12 | * | |
| 13 | * See file CREDITS for list of people who contributed to this | |
| 14 | * project. | |
| 15 | * | |
| 16 | * This program is free software\; you can redistribute it and/or | |
| 17 | * modify it under the terms of the GNU General Public License as | |
| 18 | * published by the Free Software Foundation\; either version 2 of | |
| 19 | * the License, or (at your option) any later version. | |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY\; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program\; if not, write to the Free Software | |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 29 | * MA 02111-1307 USA | |
| 30 | */ | |
| 31 | ||
| 32 | #ifndef __CONFIG_H | |
| 33 | #define __CONFIG_H | |
| 34 | ||
| 35 | /* | |
| 36 | * High Level Configuration Options | |
| 37 | */ | |
| 38 | ||
| 39 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
| 40 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
| 41 | #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ | |
| 42 | ||
| 43 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 | |
| 44 | ||
| 45 | #define BOOTFLAG_COLD 0x01 | |
| 46 | #define BOOTFLAG_WARM 0x02 | |
| 47 | ||
| 48 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 49 | ||
| 50 | /* | |
| 51 | * Serial console configuration | |
| 52 | */ | |
| 53 | #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ | |
| 54 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
| 55 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 56 | { 9600, 19200, 38400, 57600, 115200, 230400 } | |
| 57 | ||
| 58 | /* | |
| 59 | * PCI Mapping: | |
| 60 | * 0x40000000 - 0x4fffffff - PCI Memory | |
| 61 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
| 62 | */ | |
| 63 | #define CONFIG_PCI 1 | |
| 64 | #define CONFIG_PCI_PNP 1 | |
| 65 | #define CONFIG_PCI_SCAN_SHOW 1 | |
| 66 | ||
| 67 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
| 68 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
| 69 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
| 70 | ||
| 71 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
| 72 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
| 73 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
| 74 | ||
| 75 | /* | |
| 76 | * Partitions | |
| 77 | */ | |
| 78 | #define CONFIG_DOS_PARTITION | |
| 79 | #define CONFIG_BZIP2 | |
| 80 | ||
| 81 | /* | |
| 82 | * Command line configuration. | |
| 83 | */ | |
| 84 | #include <config_cmd_default.h> | |
| 85 | ||
| 86 | #define CONFIG_CMD_DFL | |
| 87 | #define CONFIG_CMD_CACHE | |
| 88 | #define CONFIG_CMD_DATE | |
| 89 | #define CONFIG_CMD_DHCP | |
| 90 | #define CONFIG_CMD_DIAG | |
| 91 | #define CONFIG_CMD_EEPROM | |
| 92 | #define CONFIG_CMD_ELF | |
| 93 | #define CONFIG_CMD_EXT2 | |
| 94 | #define CONFIG_CMD_FAT | |
| 95 | #define CONFIG_CMD_I2C | |
| 96 | #define CONFIG_CMD_IDE | |
| 97 | #define CONFIG_CMD_IRQ | |
| 98 | #define CONFIG_CMD_MII | |
| 99 | #define CONFIG_CMD_PCI | |
| 100 | #define CONFIG_CMD_PING | |
| 101 | #define CONFIG_CMD_REGINFO | |
| 102 | #define CONFIG_CMD_SAVES | |
| f1f66edf | 103 | #define CONFIG_CMD_SPI |
| 5c4fa9b4 GB |
104 | #define CONFIG_CMD_USB |
| 105 | ||
| 106 | #if (TEXT_BASE == 0xFF000000) | |
| 107 | #define CONFIG_SYS_LOWBOOT 1 | |
| 108 | #endif | |
| 109 | ||
| 110 | /* | |
| 111 | * Autobooting | |
| 112 | */ | |
| 113 | #define CONFIG_BOOTDELAY 1 | |
| 114 | ||
| 115 | #undef CONFIG_BOOTARGS | |
| 116 | ||
| 117 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 118 | "netdev=eth0\0" \ | |
| 119 | "console=ttyPSC0\0" \ | |
| 120 | "kernel_addr_r=400000\0" \ | |
| 121 | "fdt_addr_r=600000\0" \ | |
| 122 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 123 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 124 | "addip=setenv bootargs ${bootargs} " \ | |
| 125 | "ip=${ipaddr}:${serverip}:${gatewayip}:"\ | |
| 126 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
| 127 | "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\ | |
| 128 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
| 129 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 130 | "tftp ${fdt_addr_r} ${fdt_file};" \ | |
| 131 | "run nfsargs addip addcons;" \ | |
| 132 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
| 133 | "load=tftp 200000 ${u-boot}\0" \ | |
| 134 | "update=protect off FFF00000 +${filesize};" \ | |
| 135 | "erase FFF00000 +${filesize};" \ | |
| 136 | "cp.b 200000 FFF00000 ${filesize};" \ | |
| 137 | "protect on FFF00000 +${filesize}\0" \ | |
| 138 | "" | |
| 139 | ||
| f1f66edf GB |
140 | /* |
| 141 | * SPI configuration | |
| 142 | */ | |
| 143 | #define CONFIG_HARD_SPI 1 | |
| 144 | #define CONFIG_MPC52XX_SPI 1 | |
| 145 | ||
| 5c4fa9b4 GB |
146 | /* |
| 147 | * I2C configuration | |
| 148 | */ | |
| 149 | #define CONFIG_HARD_I2C 1 | |
| 150 | #define CONFIG_SYS_I2C_MODULE 1 | |
| 151 | #define CONFIG_SYS_I2C_SPEED 100000 | |
| 152 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 153 | ||
| 154 | /* | |
| 155 | * EEPROM configuration | |
| 156 | */ | |
| 157 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
| 158 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 159 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 160 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
| 161 | ||
| 162 | /* | |
| 163 | * RTC configuration | |
| 164 | */ | |
| 165 | #define CONFIG_RTC_DS1337 | |
| 166 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 167 | ||
| 168 | /* | |
| 169 | * Flash configuration | |
| 170 | */ | |
| 171 | #define CONFIG_SYS_FLASH_CFI 1 | |
| 172 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
| 173 | ||
| 174 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
| 175 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
| 176 | ||
| 177 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 178 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
| 179 | #define CONFIG_FLASH_16BIT | |
| 180 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 181 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 182 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 | |
| 183 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
| 184 | ||
| 185 | #define CONFIG_OF_LIBFDT 1 | |
| 186 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 187 | ||
| 188 | #define OF_CPU "PowerPC,5200@0" | |
| 189 | #define OF_SOC "soc5200@f0000000" | |
| 190 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 191 | ||
| 192 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 193 | #define CONFIG_MISC_INIT_R | |
| 194 | ||
| 195 | /* | |
| 196 | * Environment settings | |
| 197 | */ | |
| 198 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 199 | #if defined(CONFIG_LOWBOOT) | |
| 200 | #define CONFIG_ENV_ADDR 0xFF060000 | |
| 201 | #else /* CONFIG_LOWBOOT */ | |
| 202 | #define CONFIG_ENV_ADDR 0xFFF60000 | |
| 203 | #endif /* CONFIG_LOWBOOT */ | |
| 204 | #define CONFIG_ENV_SIZE 0x10000 | |
| 205 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 206 | #define CONFIG_ENV_OVERWRITE 1 | |
| 207 | ||
| 208 | /* | |
| 209 | * Memory map | |
| 210 | */ | |
| 211 | #define CONFIG_SYS_MBAR 0xF0000000 | |
| 212 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| 213 | #if !defined(CONFIG_SYS_LOWBOOT) | |
| 214 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
| 215 | #else | |
| 216 | #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000 | |
| 217 | #endif | |
| 218 | ||
| 219 | /* | |
| 220 | * Use SRAM until RAM will be available | |
| 221 | */ | |
| 222 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
| 223 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
| 224 | ||
| 225 | #define CONFIG_SYS_GBL_DATA_SIZE 4096 | |
| 226 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
| 227 | (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 228 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 229 | ||
| 230 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
| 231 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
| 232 | #define CONFIG_SYS_RAMBOOT 1 | |
| 233 | #endif | |
| 234 | ||
| 235 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
| 236 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) | |
| 237 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
| 238 | ||
| 239 | /* | |
| 240 | * Ethernet configuration | |
| 241 | */ | |
| 242 | #define CONFIG_MPC5xxx_FEC 1 | |
| 243 | #define CONFIG_MPC5xxx_FEC_MII100 | |
| 244 | #define CONFIG_PHY_ADDR 0x00 | |
| 245 | #define CONFIG_PHY_RESET_DELAY 1000 | |
| 246 | ||
| 247 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
| 248 | ||
| 249 | /* | |
| 250 | * GPIO configuration | |
| 251 | */ | |
| 252 | #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112 | |
| 253 | ||
| 254 | /* | |
| 255 | * Miscellaneous configurable options | |
| 256 | */ | |
| 257 | #define CONFIG_SYS_LONGHELP | |
| 258 | #define CONFIG_AUTO_COMPLETE 1 | |
| 259 | #define CONFIG_SYS_PROMPT "=> " | |
| 260 | #define CONFIG_SYS_HUSH_PARSER | |
| 261 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 262 | ||
| 263 | #define CONFIG_AUTOBOOT_KEYED | |
| 264 | #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay | |
| 265 | #define CONFIG_AUTOBOOT_DELAY_STR " " | |
| 266 | ||
| 267 | #define CONFIG_LOOPW 1 | |
| 268 | #define CONFIG_MX_CYCLIC 1 | |
| 269 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 270 | ||
| 271 | #define CONFIG_SYS_CBSIZE 1024 | |
| 272 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 273 | #define CONFIG_SYS_MAXARGS 32 | |
| 274 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 275 | ||
| 276 | #define CONFIG_SYS_ALT_MEMTEST | |
| 277 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000 | |
| 278 | #define CONFIG_SYS_MEMTEST_START 0x00010000 | |
| 279 | #define CONFIG_SYS_MEMTEST_END 0x019fffff | |
| 280 | ||
| 281 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 | |
| 282 | ||
| 283 | #define CONFIG_SYS_HZ 1000 | |
| 284 | ||
| 285 | /* | |
| 286 | * Various low-level settings | |
| 287 | */ | |
| 288 | #define CONFIG_SYS_SDRAM_CS1 1 | |
| 289 | #define CONFIG_SYS_XLB_PIPELINING 1 | |
| 290 | ||
| 291 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI | |
| 292 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
| 293 | ||
| 294 | #if defined(CONFIG_SYS_LOWBOOT) | |
| 295 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
| 296 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
| 297 | #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 | |
| 298 | #endif | |
| 299 | ||
| 300 | #define CONFIG_SYS_CS4_START 0x60000000 | |
| 301 | #define CONFIG_SYS_CS4_SIZE 0x1000 | |
| 302 | #define CONFIG_SYS_CS4_CFG 0x0008FC00 | |
| 303 | ||
| 304 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
| 305 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
| 306 | #define CONFIG_SYS_CS0_CFG 0x0002DD00 | |
| 307 | ||
| 308 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
| 309 | #define CONFIG_SYS_CS_DEADCYCLE 0x11111111 | |
| 310 | ||
| 311 | #if !defined(CONFIG_SYS_LOWBOOT) | |
| 312 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
| 313 | #else | |
| 314 | #define CONFIG_SYS_RESET_ADDRESS 0xff000100 | |
| 315 | #endif | |
| 316 | ||
| 317 | /* | |
| 318 | * USB | |
| 319 | */ | |
| 320 | #define CONFIG_USB_OHCI_NEW | |
| 321 | #define CONFIG_SYS_OHCI_BE_CONTROLLER | |
| 322 | #define CONFIG_USB_STORAGE | |
| 323 | ||
| 324 | #define CONFIG_USB_CLOCK 0x00013333 | |
| 325 | #define CONFIG_USB_CONFIG 0x00002000 | |
| 326 | ||
| 327 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 328 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
| 329 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
| 330 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
| 331 | ||
| 332 | /* | |
| 333 | * IDE/ATA | |
| 334 | */ | |
| 335 | #define CONFIG_IDE_RESET | |
| 336 | #define CONFIG_IDE_PREINIT | |
| 337 | ||
| 338 | #define CONFIG_SYS_ATA_CS_ON_I2C2 | |
| 339 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
| 340 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
| 341 | ||
| 342 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| 343 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
| 344 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
| 345 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
| 346 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
| 347 | #define CONFIG_SYS_ATA_STRIDE 4 | |
| 348 | ||
| 349 | #define CONFIG_ATAPI 1 | |
| 350 | #define CONFIG_LBA48 1 | |
| 351 | ||
| 352 | #endif /* __CONFIG_H */ |