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3ef5ebeb LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated. | |
4 | * Lokesh Vutla <lokeshvutla@ti.com> | |
5 | * | |
6 | * Configuration settings for the TI DRA7XX board. | |
3d657a05 | 7 | * See ti_omap5_common.h for omap5 common settings. |
3ef5ebeb | 8 | * |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
3ef5ebeb LV |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_DRA7XX_EVM_H | |
13 | #define __CONFIG_DRA7XX_EVM_H | |
14 | ||
f843770a SN |
15 | #include <environment/ti/dfu.h> |
16 | ||
a8017574 | 17 | #define CONFIG_DRA7XX |
7b922523 | 18 | #define CONFIG_BOARD_EARLY_INIT_F |
3ef5ebeb | 19 | |
706dd348 LV |
20 | #ifdef CONFIG_SPL_BUILD |
21 | #define CONFIG_IODELAY_RECALIBRATION | |
22 | #endif | |
23 | ||
212425b2 | 24 | #define CONFIG_VERY_BIG_RAM |
212425b2 LV |
25 | #define CONFIG_NR_DRAM_BANKS 2 |
26 | #define CONFIG_MAX_MEM_MAPPED 0x80000000 | |
27 | ||
79b079f3 | 28 | #ifndef CONFIG_QSPI_BOOT |
d3d33daf LV |
29 | /* MMC ENV related defines */ |
30 | #define CONFIG_ENV_IS_IN_MMC | |
31 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ | |
2737f011 | 32 | #define CONFIG_ENV_SIZE (128 << 10) |
d3d33daf LV |
33 | #define CONFIG_ENV_OFFSET 0xE0000 |
34 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
35 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
79b079f3 | 36 | #endif |
3ef5ebeb | 37 | |
a13cbf5f | 38 | #if (CONFIG_CONS_INDEX == 1) |
a8017574 | 39 | #define CONSOLEDEV "ttyO0" |
a13cbf5f MS |
40 | #elif (CONFIG_CONS_INDEX == 3) |
41 | #define CONSOLEDEV "ttyO2" | |
42 | #endif | |
43 | #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ | |
44 | #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ | |
45 | #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ | |
378bd1fb | 46 | #define CONFIG_BAUDRATE 115200 |
97405d84 LV |
47 | |
48 | #define CONFIG_SYS_OMAP_ABE_SYSCK | |
45dbbf29 | 49 | |
08520bf5 | 50 | #ifndef CONFIG_SPL_BUILD |
2efa79ae TR |
51 | /* Define the default GPT table for eMMC */ |
52 | #define PARTS_DEFAULT \ | |
c6afa113 | 53 | /* Linux partitions */ \ |
2efa79ae | 54 | "uuid_disk=${uuid_gpt_disk};" \ |
c6afa113 SP |
55 | "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ |
56 | /* Android partitions */ \ | |
57 | "partitions_android=" \ | |
58 | "uuid_disk=${uuid_gpt_disk};" \ | |
4886de76 SP |
59 | "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ |
60 | "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ | |
c6afa113 SP |
61 | "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ |
62 | "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ | |
4886de76 SP |
63 | "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ |
64 | "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ | |
c6afa113 SP |
65 | "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ |
66 | "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ | |
67 | "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ | |
68 | "name=system,size=768M,uuid=${uuid_gpt_system};" \ | |
69 | "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ | |
70 | "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ | |
71 | "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ | |
72 | "name=userdata,size=-,uuid=${uuid_gpt_userdata}" | |
2efa79ae | 73 | |
7a5a3e37 KVA |
74 | #define DFUARGS \ |
75 | "dfu_bufsiz=0x10000\0" \ | |
76 | DFU_ALT_INFO_MMC \ | |
77 | DFU_ALT_INFO_EMMC \ | |
5486d067 V |
78 | DFU_ALT_INFO_RAM \ |
79 | DFU_ALT_INFO_QSPI | |
234600c1 SP |
80 | #else |
81 | /* Discard fastboot in SPL build, to spare some space */ | |
82 | #undef CONFIG_FASTBOOT | |
83 | #undef CONFIG_USB_FUNCTION_FASTBOOT | |
84 | #undef CONFIG_CMD_FASTBOOT | |
85 | #undef CONFIG_ANDROID_BOOT_IMAGE | |
86 | #undef CONFIG_FASTBOOT_BUF_ADDR | |
87 | #undef CONFIG_FASTBOOT_BUF_SIZE | |
88 | #undef CONFIG_FASTBOOT_FLASH | |
08520bf5 | 89 | #endif |
be17d396 | 90 | |
cdb1808a R |
91 | #ifdef CONFIG_SPL_BUILD |
92 | #undef CONFIG_CMD_BOOTD | |
93 | #ifdef CONFIG_SPL_DFU_SUPPORT | |
94 | #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 | |
cdb1808a R |
95 | #define DFUARGS \ |
96 | "dfu_bufsiz=0x10000\0" \ | |
97 | DFU_ALT_INFO_RAM | |
98 | #endif | |
99 | #endif | |
100 | ||
3d657a05 | 101 | #include <configs/ti_omap5_common.h> |
45dbbf29 | 102 | |
2efa79ae TR |
103 | /* Enhance our eMMC support / experience. */ |
104 | #define CONFIG_CMD_GPT | |
105 | #define CONFIG_EFI_PARTITION | |
c6afa113 | 106 | #define CONFIG_RANDOM_UUID |
8065a4e8 | 107 | #define CONFIG_HSMMC2_8BIT |
2efa79ae | 108 | |
c9be62ca | 109 | /* CPSW Ethernet */ |
457bb505 | 110 | #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ |
c9be62ca M |
111 | #define CONFIG_BOOTP_DNS2 |
112 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
113 | #define CONFIG_BOOTP_GATEWAY | |
114 | #define CONFIG_BOOTP_SUBNETMASK | |
457bb505 | 115 | #define CONFIG_NET_RETRY_COUNT 10 |
457bb505 TR |
116 | #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ |
117 | #define CONFIG_MII /* Required in net/eth.c */ | |
118 | #define CONFIG_PHY_GIGE /* per-board part of CPSW */ | |
c9be62ca | 119 | #define CONFIG_PHYLIB |
39fbac91 | 120 | #define CONFIG_PHY_TI |
c9be62ca | 121 | |
247cdf04 MP |
122 | /* SPI */ |
123 | #undef CONFIG_OMAP3_SPI | |
247cdf04 | 124 | #define CONFIG_TI_SPI_MMAP |
b9612bb2 | 125 | #define CONFIG_SF_DEFAULT_SPEED 76800000 |
900e2104 | 126 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
46122960 | 127 | #define CONFIG_QSPI_QUAD_SUPPORT |
247cdf04 | 128 | |
e7af6725 M |
129 | #ifdef CONFIG_SPL_BUILD |
130 | #undef CONFIG_DM_SPI | |
131 | #undef CONFIG_DM_SPI_FLASH | |
132 | #endif | |
133 | ||
79b079f3 TR |
134 | /* |
135 | * Default to using SPI for environment, etc. | |
279dcd89 | 136 | * 0x000000 - 0x040000 : QSPI.SPL (256KiB) |
79b079f3 TR |
137 | * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) |
138 | * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) | |
139 | * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) | |
140 | * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) | |
141 | * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) | |
142 | * 0x9E0000 - 0x2000000 : USERLAND | |
143 | */ | |
144 | #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 | |
145 | #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 | |
146 | #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 | |
147 | #if defined(CONFIG_QSPI_BOOT) | |
79b079f3 TR |
148 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
149 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
150 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
151 | #define CONFIG_ENV_SIZE (64 << 10) | |
152 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ | |
153 | #define CONFIG_ENV_OFFSET 0x1C0000 | |
154 | #define CONFIG_ENV_OFFSET_REDUND 0x1D0000 | |
155 | #endif | |
156 | ||
247cdf04 | 157 | /* SPI SPL */ |
fc5e2200 | 158 | #define CONFIG_TI_EDMA3 |
247cdf04 | 159 | #define CONFIG_SPL_SPI_LOAD |
79b079f3 | 160 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 |
247cdf04 | 161 | |
b818d9ab TR |
162 | #define CONFIG_SUPPORT_EMMC_BOOT |
163 | ||
834e91af | 164 | /* USB xHCI HOST */ |
834e91af | 165 | #define CONFIG_USB_XHCI_OMAP |
834e91af DM |
166 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 |
167 | ||
168 | #define CONFIG_OMAP_USB_PHY | |
169 | #define CONFIG_OMAP_USB2PHY2_HOST | |
170 | ||
21914ee6 | 171 | /* SATA */ |
c649e3c9 | 172 | #define CONFIG_SCSI |
21914ee6 RQ |
173 | #define CONFIG_LIBATA |
174 | #define CONFIG_SCSI_AHCI | |
175 | #define CONFIG_SCSI_AHCI_PLAT | |
176 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
177 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
178 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
179 | CONFIG_SYS_SCSI_MAX_LUN) | |
180 | ||
54a97d28 | 181 | /* NAND support */ |
182 | #ifdef CONFIG_NAND | |
183 | /* NAND: device related configs */ | |
184 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
185 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
186 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
187 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT | |
188 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ | |
189 | CONFIG_SYS_NAND_PAGE_SIZE) | |
190 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
191 | /* NAND: driver related configs */ | |
192 | #define CONFIG_NAND_OMAP_GPMC | |
193 | #define CONFIG_NAND_OMAP_ELM | |
194 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
195 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW | |
196 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
197 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
198 | 10, 11, 12, 13, 14, 15, 16, 17, \ | |
199 | 18, 19, 20, 21, 22, 23, 24, 25, \ | |
200 | 26, 27, 28, 29, 30, 31, 32, 33, \ | |
201 | 34, 35, 36, 37, 38, 39, 40, 41, \ | |
202 | 42, 43, 44, 45, 46, 47, 48, 49, \ | |
203 | 50, 51, 52, 53, 54, 55, 56, 57, } | |
204 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
205 | #define CONFIG_SYS_NAND_ECCBYTES 14 | |
206 | #define MTDIDS_DEFAULT "nand0=nand.0" | |
207 | #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ | |
208 | "128k(NAND.SPL)," \ | |
209 | "128k(NAND.SPL.backup1)," \ | |
210 | "128k(NAND.SPL.backup2)," \ | |
211 | "128k(NAND.SPL.backup3)," \ | |
212 | "256k(NAND.u-boot-spl-os)," \ | |
213 | "1m(NAND.u-boot)," \ | |
214 | "128k(NAND.u-boot-env)," \ | |
215 | "128k(NAND.u-boot-env.backup1)," \ | |
216 | "8m(NAND.kernel)," \ | |
9ddef489 | 217 | "-(NAND.file-system)" |
54a97d28 | 218 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 |
219 | /* NAND: SPL related configs */ | |
220 | #ifdef CONFIG_SPL_NAND_SUPPORT | |
221 | #define CONFIG_SPL_NAND_AM33XX_BCH | |
222 | #endif | |
223 | /* NAND: SPL falcon mode configs */ | |
224 | #ifdef CONFIG_SPL_OS_BOOT | |
225 | #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/ | |
226 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ | |
227 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 | |
228 | #endif | |
229 | #endif /* !CONFIG_NAND */ | |
230 | ||
9352697a | 231 | /* Parallel NOR Support */ |
232 | #if defined(CONFIG_NOR) | |
233 | /* NOR: device related configs */ | |
234 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
235 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
236 | #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ | |
237 | /* #define CONFIG_INIT_IGNORE_ERROR */ | |
238 | #undef CONFIG_SYS_NO_FLASH | |
9352697a | 239 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
240 | #define CONFIG_SYS_FLASH_PROTECTION | |
241 | #define CONFIG_SYS_FLASH_CFI | |
242 | #define CONFIG_FLASH_CFI_DRIVER | |
243 | #define CONFIG_FLASH_CFI_MTD | |
244 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
245 | #define CONFIG_SYS_FLASH_BASE (0x08000000) | |
246 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
247 | /* Reduce SPL size by removing unlikey targets */ | |
248 | #ifdef CONFIG_NOR_BOOT | |
249 | #define CONFIG_ENV_IS_IN_FLASH | |
250 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ | |
251 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0" | |
252 | #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ | |
253 | "128k(NOR.SPL)," \ | |
254 | "128k(NOR.SPL.backup1)," \ | |
255 | "128k(NOR.SPL.backup2)," \ | |
256 | "128k(NOR.SPL.backup3)," \ | |
257 | "256k(NOR.u-boot-spl-os)," \ | |
258 | "1m(NOR.u-boot)," \ | |
259 | "128k(NOR.u-boot-env)," \ | |
260 | "128k(NOR.u-boot-env.backup1)," \ | |
261 | "8m(NOR.kernel)," \ | |
262 | "-(NOR.rootfs)" | |
263 | #define CONFIG_ENV_OFFSET 0x001c0000 | |
264 | #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 | |
265 | #endif | |
266 | #endif /* NOR support */ | |
267 | ||
25afe55d LV |
268 | /* EEPROM */ |
269 | #define CONFIG_EEPROM_CHIP_ADDRESS 0x50 | |
270 | #define CONFIG_EEPROM_BUS_ADDRESS 0 | |
271 | ||
3ef5ebeb | 272 | #endif /* __CONFIG_DRA7XX_EVM_H */ |