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eNET: General code cleanup
[people/ms/u-boot.git] / include / configs / eNET.h
CommitLineData
c620c01e
GR		 1/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
bf16500f 24#include <asm/ibmpc.h>
c620c01e
GR		 25/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
c620c01e
GR		 32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
cfbe8615
GR		 36#define CONFIG_X86
37#define CONFIG_SYS_SC520
6d83e3ac 38#define CONFIG_SYS_SC520_SSI
cfbe8615
GR		 39#define CONFIG_SHOW_BOOT_PROGRESS
40#define CONFIG_LAST_STAGE_INIT
c620c01e 41
cfbe8615
GR		 42/*-----------------------------------------------------------------------
43 * Watchdog Configuration
44 * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
c620c01e
GR		 45 * bottom (processor) board MUST be removed!
46 */
47#undef CONFIG_WATCHDOG
880c59e5 48#define CONFIG_HW_WATCHDOG
c620c01e 49
cfbe8615
GR		 50/*-----------------------------------------------------------------------
51 * Real Time Clock Configuration
52 */
53#define CONFIG_RTC_MC146818
54#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
55
56/*-----------------------------------------------------------------------
57 * Serial Configuration
58 */
bf16500f 59#define CONFIG_SERIAL_MULTI
cfbe8615 60#define CONFIG_CONS_INDEX 1
bf16500f
GR		 61#define CONFIG_SYS_NS16550
62#define CONFIG_SYS_NS16550_SERIAL
cfbe8615
GR		 63#define CONFIG_SYS_NS16550_REG_SIZE 1
64#define CONFIG_SYS_NS16550_CLK 1843200
65#define CONFIG_BAUDRATE 9600
66#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
67 9600, 19200, 38400, 115200}
68#define CONFIG_SYS_NS16550_COM1 UART0_BASE
69#define CONFIG_SYS_NS16550_COM2 UART1_BASE
70#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
71#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
bf16500f
GR		 72#define CONFIG_SYS_NS16550_PORT_MAPPED
73
cfbe8615
GR		 74/*-----------------------------------------------------------------------
75 * Video Configuration
c620c01e 76 */
cfbe8615
GR		 77#undef CONFIG_VIDEO
78#undef CONFIG_CFB_CONSOLE
c620c01e 79
c620c01e
GR		 80/*-----------------------------------------------------------------------
81 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
cfbe8615
GR		 85#define CONFIG_CMD_BDI
86#define CONFIG_CMD_BOOTD
87#define CONFIG_CMD_CONSOLE
21831001 88#define CONFIG_CMD_DATE
cfbe8615
GR		 89#define CONFIG_CMD_ECHO
90#define CONFIG_CMD_FLASH
91#define CONFIG_CMD_FPGA
92#define CONFIG_CMD_IMI
93#define CONFIG_CMD_IMLS
94#define CONFIG_CMD_IRQ
95#define CONFIG_CMD_ITEST
96#define CONFIG_CMD_LOADB
97#define CONFIG_CMD_LOADS
98#define CONFIG_CMD_MEMORY
99#define CONFIG_CMD_MISC
100#define CONFIG_CMD_NET
101#undef CONFIG_CMD_NFS
102#define CONFIG_CMD_PCI
103#define CONFIG_CMD_PING
104#define CONFIG_CMD_RUN
105#define CONFIG_CMD_SAVEENV
106#define CONFIG_CMD_SETGETDCR
107#define CONFIG_CMD_SOURCE
108#define CONFIG_CMD_XIMG
109
110#define CONFIG_BOOTDELAY 15
111#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
c620c01e
GR		 112
113#if defined(CONFIG_CMD_KGDB)
cfbe8615
GR		 114#define CONFIG_KGDB_BAUDRATE 115200
115#define CONFIG_KGDB_SER_INDEX 2
c620c01e
GR		 116#endif
117
118/*
119 * Miscellaneous configurable options
120 */
cfbe8615
GR		 121#define CONFIG_SYS_LONGHELP
122#define CONFIG_SYS_PROMPT "boot > "
123#define CONFIG_SYS_CBSIZE 256
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
125 sizeof(CONFIG_SYS_PROMPT) + \
126 16)
127#define CONFIG_SYS_MAXARGS 16
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
c620c01e 129
cfbe8615
GR		 130#define CONFIG_SYS_MEMTEST_START 0x00100000
131#define CONFIG_SYS_MEMTEST_END 0x01000000
132#define CONFIG_SYS_LOAD_ADDR 0x100000
133#define CONFIG_SYS_HZ 1000
c620c01e 134
c620c01e
GR		 135/*-----------------------------------------------------------------------
136 * SDRAM Configuration
137 */
cfbe8615
GR		 138#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
139#define CONFIG_NR_DRAM_BANKS 4
c620c01e
GR		 140
141/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
142#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
143#undef CONFIG_SYS_SDRAM_REFRESH_RATE
144#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
145#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
146#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
147
148/*-----------------------------------------------------------------------
149 * CPU Features
150 */
cfbe8615
GR		 151#define CONFIG_SYS_SC520_HIGH_SPEED 0
152#define CONFIG_SYS_SC520_RESET
153#define CONFIG_SYS_SC520_TIMER
154#undef CONFIG_SYS_GENERIC_TIMER
abf0cd3d 155#define CONFIG_SYS_PCAT_INTERRUPTS
cfbe8615 156#define CONFIG_SYS_NUM_IRQS 16
c620c01e
GR		 157
158/*-----------------------------------------------------------------------
cfbe8615
GR		 159 * Memory organization:
160 * 32kB Stack
161 * 256kB Monitor
c620c01e 162 */
cfbe8615
GR		 163#define CONFIG_SYS_STACK_SIZE 0x8000
164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
165#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
166#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
c620c01e
GR		 167
168/* allow to overwrite serial and ethaddr */
169#define CONFIG_ENV_OVERWRITE
170
cfbe8615
GR		 171/*-----------------------------------------------------------------------
172 * FLASH configuration
173 * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
174 * 16MB StrataFlash #1 @ 0x10000000
175 * 16MB StrataFlash #2 @ 0x11000000
176 */
177#define CONFIG_FLASH_CFI_DRIVER
c620c01e 178#define CONFIG_FLASH_CFI_LEGACY
cfbe8615
GR		 179#define CONFIG_SYS_FLASH_CFI
180#define CONFIG_SYS_MAX_FLASH_BANKS 3
181#define CONFIG_SYS_FLASH_BASE 0x38000000
182#define CONFIG_SYS_FLASH_BASE_1 0x10000000
183#define CONFIG_SYS_FLASH_BASE_2 0x11000000
184#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
185 CONFIG_SYS_FLASH_BASE_1, \
186 CONFIG_SYS_FLASH_BASE_2}
c620c01e 187#define CONFIG_SYS_FLASH_EMPTY_INFO
6fd445c3 188#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
cfbe8615
GR		 189#define CONFIG_SYS_MAX_FLASH_SECT 128
190#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
c620c01e 191#define CONFIG_SYS_FLASH_LEGACY_512Kx8
cfbe8615
GR		 192#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
193#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
194/*-----------------------------------------------------------------------
195 * Environment configuration
196 */
197#define CONFIG_ENV_IS_IN_FLASH
198#define CONFIG_ENV_SECT_SIZE 0x20000
199#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
200#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
f3a8d6b2 201/* Redundant Copy */
cfbe8615
GR		 202#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
203 CONFIG_ENV_SECT_SIZE)
204#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
205
206/*-----------------------------------------------------------------------
207 * PCI configuration
208 */
209#define CONFIG_PCI
210#define CONFIG_PCI_PNP
211#define CONFIG_SYS_FIRST_PCI_IRQ 10
212#define CONFIG_SYS_SECOND_PCI_IRQ 9
213#define CONFIG_SYS_THIRD_PCI_IRQ 11
214#define CONFIG_SYS_FORTH_PCI_IRQ 15
215
216/*-----------------------------------------------------------------------
8fd80563
GR		 217 * Network device (TRL8100B) support
218 */
219#define CONFIG_NET_MULTI
220#define CONFIG_RTL8139
221
420c7c05
GR		 222/*-----------------------------------------------------------------------
223 * BOOTCS Control (for AM29LV040B-120JC)
224 *
225 * 000 0 00 0 000 11 0 011 }- 0x0033
226 * \ / | \| | \ / \| | \ /
227 * | | | | | | | |
228 * | | | | | | | +---- 3 Wait States (First Access)
229 * | | | | | | +------- Reserved
230 * | | | | | +--------- 3 Wait States (Subsequent Access)
231 * | | | | +------------- Reserved
232 * | | | +---------------- Non-Paged Mode
233 * | | +------------------ 8 Bit Wide
234 * | +--------------------- GP Bus
235 * +------------------------ Reserved
236 */
237#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
238
239/*-----------------------------------------------------------------------
240 * ROMCS Control (for E28F128J3A-150 StrataFlash)
241 *
242 * 000 0 01 1 000 01 0 101 }- 0x0615
243 * \ / | \| | \ / \| | \ /
244 * | | | | | | | |
245 * | | | | | | | +---- 5 Wait States (First Access)
246 * | | | | | | +------- Reserved
247 * | | | | | +--------- 1 Wait State (Subsequent Access)
248 * | | | | +------------- Reserved
249 * | | | +---------------- Paged Mode
250 * | | +------------------ 16 Bit Wide
251 * | +--------------------- GP Bus
252 * +------------------------ Reserved
253 */
254#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
255#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
256
257/*-----------------------------------------------------------------------
258 * SC520 General Purpose Bus configuration
259 *
260 * Chip Select Offset 1 Clock Cycle
261 * Chip Select Pulse Width 8 Clock Cycles
262 * Chip Select Read Offset 2 Clock Cycles
263 * Chip Select Read Width 6 Clock Cycles
264 * Chip Select Write Offset 2 Clock Cycles
265 * Chip Select Write Width 6 Clock Cycles
266 * Chip Select Recovery Time 2 Clock Cycles
267 *
268 * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
269 *
270 * |<-------------General Purpose Bus Cycle---------------->|
271 * | |
272 * ----------------------\__________________/------------------
273 * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
274 *
275 * ------------------------\_______________/-------------------
276 * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
277 *
278 * --------------------------\_______________/-----------------
279 * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
280 *
281 * ________/-----------\_______________________________________
282 * |<--->|<--------->|
283 * ^ ^
284 * (GPALEOFF + 1) |
285 * |
286 * (GPALEW + 1)
287 */
288#define CONFIG_SYS_SC520_GPCSOFF 0x00
289#define CONFIG_SYS_SC520_GPCSPW 0x07
290#define CONFIG_SYS_SC520_GPRDOFF 0x01
291#define CONFIG_SYS_SC520_GPRDW 0x05
292#define CONFIG_SYS_SC520_GPWROFF 0x01
293#define CONFIG_SYS_SC520_GPWRW 0x05
294#define CONFIG_SYS_SC520_GPCSRT 0x01
295
296/*-----------------------------------------------------------------------
297 * SC520 Programmable I/O configuration
298 *
299 * Pin Mode Dir. Description
300 * ----------------------------------------------------------------------
301 * PIO0 PIO Output Unused
302 * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
303 * PIO2 PIO Output Auxiliary power output enable
304 * PIO3 GPAEN Output GP Bus Address Enable
305 * PIO4 PIO Output Top Board Enable (active low)
306 * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
307 * PIO6 PIO Input Data output of Power Supply ADC
308 * PIO7 PIO Output Clock input to Power Supply ADC
309 * PIO8 PIO Output Chip Select input of Power Supply ADC
310 * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
311 * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
312 * PIO11 PIO Input StrataFlash 1 Status
313 * PIO12 PIO Input StrataFlash 2 Status
314 * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
315 * PIO14 PIO Input Low Input Voltage Warning (active low)
316 * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
317 * PIO16 PIO Input Power Fail
318 * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
319 * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
320 * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
321 * PIO20 GPIRQ3 Input UART D IRQ
322 * PIO21 GPIRQ2 Input UART C IRQ
323 * PIO22 GPIRQ1 Input UART B IRQ
324 * PIO23 GPIRQ0 Input UART A IRQ
325 * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
326 * PIO25 PIO Input Battery OK Indication
327 * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
328 * PIO27 GPCS0# Output SRAM 1 Chip Select
329 * PIO28 PIO Input Top Board UART CTS
330 * PIO29 PIO Output FPGA Program Mode (active low)
331 * PIO30 PIO Input FPGA Initialised (active low)
332 * PIO31 PIO Input FPGA Done (active low)
333 */
334#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
335#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
336#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
337#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
338
339/*-----------------------------------------------------------------------
340 * PIO Pin defines
341 */
342#define CONFIG_SYS_ENET_AUX_PWR 0x0004
343#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
344#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
345#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
346#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
347#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
348#define CONFIG_SYS_ENET_SF1_MODE 0x0200
349#define CONFIG_SYS_ENET_SF2_MODE 0x0400
350#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
351#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
352#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
353#define CONFIG_SYS_ENET_WATCHDOG 0x8000
354
355#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
356#define CONFIG_SYS_ENET_BAT_OK 0x0200
357#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
358#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
359#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
360#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
361
362/*-----------------------------------------------------------------------
363 * Chip Select Pin Function Select
364 *
365 * 1 1 1 1 1 0 0 0 }- 0xf8
366 * | | | | | | | |
367 * | | | | | | | +--- Reserved
368 * | | | | | | +----- GPCS1_SEL = ROMCS1#
369 * | | | | | +------- GPCS2_SEL = ROMCS2#
370 * | | | | +--------- GPCS3_SEL = GPCS3
371 * | | | +----------- GPCS4_SEL = GPCS4
372 * | | +------------- GPCS5_SEL = GPCS5
373 * | +--------------- GPCS6_SEL = GPCS6
374 * +----------------- GPCS7_SEL = GPCS7
375 */
376#define CONFIG_SYS_SC520_CSPFS 0xf8
377
378/*-----------------------------------------------------------------------
379 * Clock Select (CLKTIMER[CLKTEST] pin)
380 *
381 * 0 111 00 1 0 }- 0x72
382 * | \ / \| | |
383 * | | | | +--- Pin Disabled
384 * | | | +----- Pin is an output
385 * | | +------- Reserved
386 * | +----------- Disabled (pin stays Low)
387 * +-------------- Reserved
388 */
389#define CONFIG_SYS_SC520_CLKSEL 0x72
390
391/*-----------------------------------------------------------------------
392 * Address Decode Control
393 *
394 * 0 00 0 0 0 0 0 }- 0x00
395 * | \| | | | | |
396 * | | | | | | +--- Integrated UART 1 is enabled
397 * | | | | | +----- Integrated UART 2 is enabled
398 * | | | | +------- Integrated RTC is enabled
399 * | | | +--------- Reserved
400 * | | +----------- I/O Hole accesses are forwarded to the external GP bus
401 * | +------------- Reserved
402 * +---------------- Write-protect violations do not generate an IRQ
403 */
404#define CONFIG_SYS_SC520_ADDDECCTL 0x00
405
406/*-----------------------------------------------------------------------
407 * UART Control
408 *
409 * 00000 1 1 1 }- 0x07
410 * \___/ | | |
411 * | | | +--- Transmit TC interrupt enable
412 * | | +----- Receive TC interrupt enable
413 * | +------- 1.8432 MHz
414 * +----------- Reserved
415 */
416#define CONFIG_SYS_SC520_UART1CTL 0x07
417#define CONFIG_SYS_SC520_UART2CTL 0x07
418
419/*-----------------------------------------------------------------------
420 * System Arbiter Control
421 *
422 * 00000 1 1 0 }- 0x06
423 * \___/ | | |
424 * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
425 * | | +----- The system arbiter operates in concurrent mode
426 * | +------- Park the PCI bus on the last master that acquired the bus
427 * +----------- Reserved
428 */
429#define CONFIG_SYS_SC520_SYSARBCTL 0x06
430
431/*-----------------------------------------------------------------------
432 * System Arbiter Master Enable
433 *
434 * 00000000000 0 0 0 1 1 }- 0x06
435 * \_________/ | | | | |
436 * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
437 * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
438 * | | | +------- PCI master REQ2 disabled
439 * | | +--------- PCI master REQ3 disabled
440 * | +----------- PCI master REQ4 disabled
441 * +------------------ Reserved
442 */
443#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
444
445/*-----------------------------------------------------------------------
446 * System Arbiter Master Enable
447 *
448 * 0 0000 0 00 0000 1 000 }- 0x06
449 * | \__/ | \| \__/ | \_/
450 * | | | | | | +---- Reserved
451 * | | | | | +------- Enable CPU-to-PCI bus write posting
452 * | | | | +---------- Reserved
453 * | | | +-------------- PCI bus reads to SDRAM are not automatically
454 * | | | retried
455 * | | +----------------- Target read FIFOs are not snooped during write
456 * | | transactions
457 * | +-------------------- Reserved
458 * +------------------------ Deassert the PCI bus reset signal
459 */
460#define CONFIG_SYS_SC520_HBCTL 0x08
461
462/*-----------------------------------------------------------------------
463 * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
464 * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
465 * \ / | | | | \----+----/ \-----+------/
466 * | | | | | | +---------- Start at 0x38000000
467 * | | | | | +----------------------- 512kB Region Size
468 * | | | | | ((7 + 1) * 64kB)
469 * | | | | +------------------------------ 64kB Page Size
470 * | | | +-------------------------------- Writes Enabled (So it can be
471 * | | | reprogrammed!)
472 * | | +---------------------------------- Caching Disabled
473 * | +------------------------------------ Execution Enabled
474 * +--------------------------------------- BOOTCS
475 */
476#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
477
478/*-----------------------------------------------------------------------
479 * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
480 *
481 * 001 110 0 000100000 0001000000000000 }- 0x38201000
482 * \ / \ / | \---+---/ \------+-------/
483 * | | | | +----------- Start at 0x00001000
484 * | | | +------------------------ 33 Bytes (0x20 + 1)
485 * | | +------------------------------ Ignored
486 * | +--------------------------------- GPCS6
487 * +------------------------------------- GP Bus I/O
488 */
489#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
490
491/*-----------------------------------------------------------------------
492 * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
493 * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
494 *
495 * 010 101 0 0000000 100000000000000000 }- 0x54020000
496 * 010 111 0 0000000 100000000000000001 }- 0x5c020001
497 * \ / \ / | \--+--/ \-------+--------/
498 * | | | | +------------ Start at 0x200000000
499 * | | | | 0x200010000
500 * | | | +------------------------- 4kB Region Size
501 * | | | ((0 + 1) * 4kB)
502 * | | +------------------------------ 4k Page Size
503 * | +--------------------------------- GPCS5
504 * | GPCS7
505 * +------------------------------------- GP Bus Memory
506 */
507#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
508#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
509
510/*-----------------------------------------------------------------------
511 * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
512 * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
513 * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
514 * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
515 *
516 * 001 000 0 000000111 0001001111111000 }- 0x200713f8
517 * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
518 * 001 011 0 000000111 0001001011111000 }- 0x300711f8
519 * 001 011 0 000000111 0001001011111000 }- 0x340710f8
520 * \ / \ / | \---+---/ \------+-------/
521 * | | | | +----------- Start at 0x013f8
522 * | | | | 0x012f8
523 * | | | | 0x011f8
524 * | | | | 0x010f8
525 * | | | +------------------------ 33 Bytes (32 + 1)
526 * | | +------------------------------ Ignored
527 * | +--------------------------------- GPCS6
528 * +------------------------------------- GP Bus I/O
529 */
530#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
531#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
532#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
533#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
534
535/*-----------------------------------------------------------------------
536 * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
537 * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
538 *
539 * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
540 * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
541 * \ / | | | | \----+----/ \-----+------/
542 * | | | | | | +---------- Start at 0x10000000
543 * | | | | | | 0x11000000
544 * | | | | | +----------------------- 16MB Region Size
545 * | | | | | ((255 + 1) * 64kB)
546 * | | | | +------------------------------ 64kB Page Size
547 * | | | +-------------------------------- Writes Enabled
548 * | | +---------------------------------- Caching Disabled
549 * | +------------------------------------ Execution Enabled
550 * +--------------------------------------- ROMCS1
551 * ROMCS2
552 */
553#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
554#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
555
556/*-----------------------------------------------------------------------
557 * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
558 * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
559 *
560 * 010 000 1 00000001111 01100100000000 }- 0x4203d900
561 * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
562 * \ / \ / | \----+----/ \-----+------/
563 * | | | | +---------- Start at 0x19000000
564 * | | | | 0x19100000
565 * | | | +----------------------- 1MB Region Size
566 * | | | ((15 + 1) * 64kB)
567 * | | +------------------------------ 64kB Page Size
568 * | +--------------------------------- GPCS0
569 * | GPCS3
570 * +------------------------------------- GP Bus Memory
571 */
572#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
573#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
574
575/*-----------------------------------------------------------------------
576 * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
577 *
578 * 010 100 0 00000000 11000000100000000 }- 0x50018100
579 * \ / \ / | \---+--/ \-------+-------/
580 * | | | | +----------- Start at 0x18100000
581 * | | | +------------------------ 4kB Region Size
582 * | | | ((0 + 1) * 4kB)
583 * | | +------------------------------ 4kB Page Size
584 * | +--------------------------------- GPCS4
585 * +------------------------------------- GP Bus Memory
586 */
587#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
588
c620c01e 589#endif /* __CONFIG_H */
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