[people/ms/u-boot.git] / include / configs / eXalion.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

/* #define CONFIG_MPC8240	   1 */
#define CONFIG_MPC8245		1
#define CONFIG_EXALION		1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#if defined (CONFIG_MPC8240)
    /* #warning	 ---------- eXalion with MPC8240 --------------- */
#elif defined (CONFIG_MPC8245)
    /* #warning	 ++++++++++ eXalion with MPC8245 +++++++++++++++ */
#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
#else
#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
/* older kernels need clock in MHz newer in Hz */
					/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz	    */
#undef CONFIG_CLOCKS_IN_MHZ

#define CONFIG_BOOTDELAY	10


						    /*#define CONFIG_DRAM_SPEED	      66   */ /* MHz			     */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_PCI


/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1	/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		8	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
#define CONFIG_MISC_INIT_R	1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
					     /* return real value.		*/

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_DATA_SIZE	128

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET


#if defined (CONFIG_MPC8240)
#define CONFIG_SYS_FLASH_BASE	    0xFFE00000
#define CONFIG_SYS_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
#elif defined (CONFIG_MPC8245)
#define CONFIG_SYS_FLASH_BASE	    0xFFC00000
#define CONFIG_SYS_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of one Flash sector */
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE	/* Use one Flash sector for environment	*/
#define CONFIG_ENV_ADDR		0xFFFC0000
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning  */

#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_ALT_MEMTEST		1	/* use real memory test	    */
#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	    */
#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

/* #define CONFIG_SYS_ISA_MEM		   0xFD000000 */
#define CONFIG_SYS_ISA_IO		0xFE000000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
#define FLASH_BASE1_PRELIM	0


/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/


/*-----------------------------------------------------------------------
 * PCI stuff
 */
#define CONFIG_PCI		1	/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#undef	CONFIG_PCI_PNP


#define CONFIG_EEPRO100		1

#define PCI_ENET0_MEMADDR	0x80000000	/* Intel 82559ER */
#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET1_MEMADDR	0x81000000	/* Intel 82559ER */
#define PCI_ENET1_IOADDR	0x81000000
#define PCI_ENET2_MEMADDR	0x82000000	/* Broadcom BCM569xx */
#define PCI_ENET2_IOADDR	0x82000000
#define PCI_ENET3_MEMADDR	0x83000000	/* Broadcom BCM56xx */
#define PCI_ENET3_IOADDR	0x83000000

/*-----------------------------------------------------------------------
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550		1
#define CONFIG_SYS_NS16550_SERIAL	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		38400

#define CONFIG_SYS_NS16550_REG_SIZE	1

#if (CONFIG_CONS_INDEX == 1)
#define CONFIG_SYS_NS16550_CLK		1843200 /* COM1 only !	*/
#else
#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
#endif

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + 0x3F8)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#undef	CONFIG_SYS_I2C_SOFT		/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/

				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */

#if defined (CONFIG_MPC8245)
/* Bit-field values for PMCR2.							*/
#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
#define CONFIG_SYS_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
#endif

/* Bit-field values for MIOCR1.							*/
#if !defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
#endif
/* Bit-field values for MIOCR2.							*/
#define CONFIG_SYS_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
					/*	- note bottom 3 bits MUST be 0	*/
#endif

/* Bit-field values for MCCR1.							*/
#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL	       11	/*rom/flash access time			*/

/* Bit-field values for MCCR2.							*/
#define CONFIG_SYS_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_REFINT		1300	/* no of clock cycles between CBR	*/
#else  /* refresh cycles */
#define CONFIG_SYS_REFINT		750
#endif

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_BSTOPRE		1023
#else
#define CONFIG_SYS_BSTOPRE		250
#endif

/* Bit-field values for MCCR3.							*/
/* the following are for SDRAM only						*/

#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_REFREC		9	/* Refresh to activate interval		*/
#else
#define CONFIG_SYS_REFREC		5	/* Refresh to activate interval		*/
#endif
#if defined (CONFIG_MPC8240)
#define CONFIG_SYS_RDLAT		2	/* data latency from read command	*/
#endif

/* Bit-field values for MCCR4.	*/
#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		7	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		5	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#else
#if 0
#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
#endif
#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#endif
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
#define CONFIG_SYS_REGDIMM		0
#if defined (CONFIG_MPC8240)
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   0
#elif defined (CONFIG_MPC8245)
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
#define CONFIG_SYS_EXTROM		    0
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif


/*-----------------------------------------------------------------------
 memory bank settings
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x3ff00000
#define CONFIG_SYS_BANK1_END		0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0

/*-----------------------------------------------------------------------
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#if defined (CONFIG_MPC8240)
#define CONFIG_SYS_ODCR		0xDF	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#elif defined (CONFIG_MPC8245)
#if defined (CONFIG_133MHZ_DRAM)
#define CONFIG_SYS_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
#else
#define CONFIG_SYS_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
#endif
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/*-----------------------------------------------------------------------
 * Block Address Translation (BAT) register settings.
 */
/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */
#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 */
#define CONFIG_SYS_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE   (CONFIG_SYS_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR   CONFIG_SYS_ISA_IO	/* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
#define CONFIG_SYS_ATA_DATA_OFFSET 0	/* data reg offset  */
#define CONFIG_SYS_ATA_REG_OFFSET  0	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET  0x200	/* alternate register offset */

#define CONFIG_ATAPI

#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */

/*-----------------------------------------------------------------------
 * DISK Partition support
 */
#define CONFIG_DOS_PARTITION

/*-----------------------------------------------------------------------
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#endif /* __CONFIG_H */
Commit	Line	Data
80885a9d WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
80885a9d WD	6	*/
	7
	8	/* ------------------------------------------------------------------------- */
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
80885a9d WD	22	/* #define CONFIG_MPC8240 1 */
	23	#define CONFIG_MPC8245 1
	24	#define CONFIG_EXALION 1
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	27
80885a9d WD	28	#if defined (CONFIG_MPC8240)
	29	/* #warning ---------- eXalion with MPC8240 --------------- */
	30	#elif defined (CONFIG_MPC8245)
	31	/* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */
	32	#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
	33	#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
	34	#else
	35	#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	36	#endif
	37	/* older kernels need clock in MHz newer in Hz */
132ba5fd	38	/* #define CONFIG_CLOCKS_IN_MHZ 1 / / clocks passsed to Linux in MHz */
80885a9d WD	39	#undef CONFIG_CLOCKS_IN_MHZ
	40
	41	#define CONFIG_BOOTDELAY 10
	42
	43
132ba5fd	44	/#define CONFIG_DRAM_SPEED 66 / /* MHz */
80885a9d	45
80ff4f99 JL	46	/*
	47	* BOOTP options
	48	*/
	49	#define CONFIG_BOOTP_BOOTFILESIZE
	50	#define CONFIG_BOOTP_BOOTPATH
	51	#define CONFIG_BOOTP_GATEWAY
	52	#define CONFIG_BOOTP_HOSTNAME
	53
	54
1bec3d30 JL	55	/*
	56	* Command line configuration.
	57	*/
	58	#include <config_cmd_default.h>
80885a9d	59
1bec3d30 JL	60	#define CONFIG_CMD_FLASH
	61	#define CONFIG_CMD_SDRAM
	62	#define CONFIG_CMD_I2C
	63	#define CONFIG_CMD_IDE
	64	#define CONFIG_CMD_FAT
bdab39d3	65	#define CONFIG_CMD_SAVEENV
1bec3d30	66	#define CONFIG_CMD_PCI
80885a9d WD	67
	68
	69	/*-----------------------------------------------------------------------
	70	* Miscellaneous configurable options
	71	*/
6d0f6bcf	72	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	73	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	74	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	75	#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
	76	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	77	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
80885a9d WD	78	#define CONFIG_MISC_INIT_R 1
	79
	80	/*-----------------------------------------------------------------------
	81	* Start addresses for the final memory configuration
	82	* (Set up by the startup code)
6d0f6bcf	83	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
80885a9d	84	*/
6d0f6bcf JCPV	85	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	86	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */
80885a9d WD	87	/* return real value. */
80885a9d WD	88
6d0f6bcf	89	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
80885a9d	90
6d0f6bcf JCPV	91	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	92	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
14d0a02a	93	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
80885a9d WD	94
	95	/*-----------------------------------------------------------------------
	96	* Definitions for initial stack pointer and data area
	97	*/
6d0f6bcf	98	#define CONFIG_SYS_INIT_DATA_SIZE 128
80885a9d	99
6d0f6bcf	100	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982 WD	101	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
553f0982 WD	102	#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
80885a9d	103
25ddd1fb	104	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	105	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
80885a9d WD	106
	107
	108	#if defined (CONFIG_MPC8240)
6d0f6bcf JCPV	109	#define CONFIG_SYS_FLASH_BASE 0xFFE00000
6d0f6bcf JCPV	110	#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */
80885a9d	111	#elif defined (CONFIG_MPC8245)
6d0f6bcf JCPV	112	#define CONFIG_SYS_FLASH_BASE 0xFFC00000
6d0f6bcf JCPV	113	#define CONFIG_SYS_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */
80885a9d WD	114	#else
	115	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	116	#endif
	117
5a1aceb0	118	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	119	#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */
1bce2aeb	120	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Use one Flash sector for environment */
0e8d1586 JCPV	121	#define CONFIG_ENV_ADDR 0xFFFC0000
0e8d1586 JCPV	122	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
80885a9d	123
6d0f6bcf	124	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
80885a9d	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
	127	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
	128	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
80885a9d	129
6d0f6bcf	130	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
80885a9d	131
6d0f6bcf JCPV	132	/* #define CONFIG_SYS_ISA_MEM 0xFD000000 */
6d0f6bcf JCPV	133	#define CONFIG_SYS_ISA_IO 0xFE000000
80885a9d WD	134
	135	/*-----------------------------------------------------------------------
	136	* FLASH organization
	137	*/
6d0f6bcf JCPV	138	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	139	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
80885a9d	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	142	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
80885a9d	143
6d0f6bcf	144	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE
80885a9d WD	145	#define FLASH_BASE1_PRELIM 0
	146
	147
	148	/*-----------------------------------------------------------------------
	149	* FLASH and environment organization
	150	*/
	151
6d0f6bcf	152	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	153	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	154	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	155	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	156	#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
	157	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
	158	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
80885a9d WD	159
	160
	161	/*-----------------------------------------------------------------------
	162	* PCI stuff
	163	*/
	164	#define CONFIG_PCI 1 /* include pci support */
842033e6	165	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
80885a9d WD	166	#undef CONFIG_PCI_PNP
80885a9d WD	167
80885a9d WD	168
	169	#define CONFIG_EEPRO100 1
	170
	171	#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */
	172	#define PCI_ENET0_IOADDR 0x80000000
	173	#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */
	174	#define PCI_ENET1_IOADDR 0x81000000
	175	#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */
	176	#define PCI_ENET2_IOADDR 0x82000000
	177	#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */
	178	#define PCI_ENET3_IOADDR 0x83000000
	179
	180	/*-----------------------------------------------------------------------
	181	* NS16550 Configuration
	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_NS16550 1
6d0f6bcf JCPV	184	#define CONFIG_SYS_NS16550_SERIAL 1
80885a9d WD	185
	186	#define CONFIG_CONS_INDEX 1
	187	#define CONFIG_BAUDRATE 38400
	188
6d0f6bcf	189	#define CONFIG_SYS_NS16550_REG_SIZE 1
80885a9d WD	190
80885a9d WD	191	#if (CONFIG_CONS_INDEX == 1)
6d0f6bcf	192	#define CONFIG_SYS_NS16550_CLK 1843200 /* COM1 only ! */
80885a9d	193	#else
6d0f6bcf	194	#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
80885a9d WD	195	#endif
80885a9d WD	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + 0x3F8)
	198	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500)
	199	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4600)
80885a9d WD	200
	201	/*-----------------------------------------------------------------------
	202	* select i2c support configuration
	203	*
	204	* Supported configurations are {none, software, hardware} drivers.
	205	* If the software driver is chosen, there are some additional
	206	* configuration items that the driver uses to drive the port pins.
	207	*/
	208	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ea818dbb	209	#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
6d0f6bcf JCPV	210	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	211	#define CONFIG_SYS_I2C_SLAVE 0x7F
80885a9d WD	212
	213	/*-----------------------------------------------------------------------
	214	* Low Level Configuration Settings
	215	* (address mappings, register initial values, etc.)
	216	* You should know what you are doing if you make changes here.
	217	*/
80885a9d WD	218
	219	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	220	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
	221
132ba5fd	222	/#define CONFIG_133MHZ_DRAM 1 / /* For 133 MHZ DRAM only !!!!!!!!!!! */
80885a9d WD	223
	224	#if defined (CONFIG_MPC8245)
	225	/* Bit-field values for PMCR2. */
	226	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf JCPV	227	#define CONFIG_SYS_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */
6d0f6bcf JCPV	228	#define CONFIG_SYS_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */
80885a9d WD	229	#endif
	230
	231	/* Bit-field values for MIOCR1. */
	232	#if !defined (CONFIG_133MHZ_DRAM)
6d0f6bcf	233	#define CONFIG_SYS_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */
80885a9d WD	234	#endif
80885a9d WD	235	/* Bit-field values for MIOCR2. */
6d0f6bcf	236	#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */
80885a9d WD	237	/* - note bottom 3 bits MUST be 0 */
	238	#endif
	239
	240	/* Bit-field values for MCCR1. */
6d0f6bcf JCPV	241	#define CONFIG_SYS_ROMNAL 7 /rom/flash next access time /
6d0f6bcf JCPV	242	#define CONFIG_SYS_ROMFAL 11 /rom/flash access time /
80885a9d WD	243
80885a9d WD	244	/* Bit-field values for MCCR2. */
6d0f6bcf	245	#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
80885a9d	246	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf	247	#define CONFIG_SYS_REFINT 1300 /* no of clock cycles between CBR */
80885a9d	248	#else /* refresh cycles */
6d0f6bcf	249	#define CONFIG_SYS_REFINT 750
80885a9d WD	250	#endif
	251
	252	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
	253	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf	254	#define CONFIG_SYS_BSTOPRE 1023
80885a9d	255	#else
6d0f6bcf	256	#define CONFIG_SYS_BSTOPRE 250
80885a9d WD	257	#endif
	258
	259	/* Bit-field values for MCCR3. */
	260	/* the following are for SDRAM only */
	261
	262	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf	263	#define CONFIG_SYS_REFREC 9 /* Refresh to activate interval */
80885a9d	264	#else
6d0f6bcf	265	#define CONFIG_SYS_REFREC 5 /* Refresh to activate interval */
80885a9d WD	266	#endif
80885a9d WD	267	#if defined (CONFIG_MPC8240)
6d0f6bcf	268	#define CONFIG_SYS_RDLAT 2 /* data latency from read command */
80885a9d WD	269	#endif
	270
	271	/* Bit-field values for MCCR4. */
	272	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf JCPV	273	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	274	#define CONFIG_SYS_ACTTOPRE 7 /* Activate to Precharge interval */
	275	#define CONFIG_SYS_ACTORW 5 /* Activate to R/W */
	276	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
80885a9d WD	277	#else
80885a9d WD	278	#if 0
6d0f6bcf JCPV	279	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	280	#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
	281	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	282	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
80885a9d	283	#endif
6d0f6bcf JCPV	284	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	285	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	286	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	287	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
80885a9d	288	#endif
6d0f6bcf JCPV	289	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	290	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
	291	#define CONFIG_SYS_REGDIMM 0
80885a9d	292	#if defined (CONFIG_MPC8240)
6d0f6bcf	293	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 0
80885a9d	294	#elif defined (CONFIG_MPC8245)
6d0f6bcf JCPV	295	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
6d0f6bcf JCPV	296	#define CONFIG_SYS_EXTROM 0
80885a9d WD	297	#else
	298	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	299	#endif
	300
	301
	302	/*-----------------------------------------------------------------------
	303	memory bank settings
	304	* only bits 20-29 are actually used from these vales to set the
	305	* start/end address the upper two bits will be 0, and the lower 20
	306	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	307	* end address
	308	*/
6d0f6bcf JCPV	309	#define CONFIG_SYS_BANK0_START 0x00000000
	310	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	311	#define CONFIG_SYS_BANK0_ENABLE 1
	312	#define CONFIG_SYS_BANK1_START 0x3ff00000
	313	#define CONFIG_SYS_BANK1_END 0x3fffffff
	314	#define CONFIG_SYS_BANK1_ENABLE 0
	315	#define CONFIG_SYS_BANK2_START 0x3ff00000
	316	#define CONFIG_SYS_BANK2_END 0x3fffffff
	317	#define CONFIG_SYS_BANK2_ENABLE 0
	318	#define CONFIG_SYS_BANK3_START 0x3ff00000
	319	#define CONFIG_SYS_BANK3_END 0x3fffffff
	320	#define CONFIG_SYS_BANK3_ENABLE 0
	321	#define CONFIG_SYS_BANK4_START 0x00000000
	322	#define CONFIG_SYS_BANK4_END 0x00000000
	323	#define CONFIG_SYS_BANK4_ENABLE 0
	324	#define CONFIG_SYS_BANK5_START 0x00000000
	325	#define CONFIG_SYS_BANK5_END 0x00000000
	326	#define CONFIG_SYS_BANK5_ENABLE 0
	327	#define CONFIG_SYS_BANK6_START 0x00000000
	328	#define CONFIG_SYS_BANK6_END 0x00000000
	329	#define CONFIG_SYS_BANK6_ENABLE 0
	330	#define CONFIG_SYS_BANK7_START 0x00000000
	331	#define CONFIG_SYS_BANK7_END 0x00000000
	332	#define CONFIG_SYS_BANK7_ENABLE 0
80885a9d WD	333
	334	/*-----------------------------------------------------------------------
	335	* Memory bank enable bitmask, specifying which of the banks defined above
	336	are actually present. MSB is for bank #7, LSB is for bank #0.
	337	*/
6d0f6bcf	338	#define CONFIG_SYS_BANK_ENABLE 0x01
80885a9d WD	339
80885a9d WD	340	#if defined (CONFIG_MPC8240)
6d0f6bcf	341	#define CONFIG_SYS_ODCR 0xDF /* configures line driver impedances, */
80885a9d WD	342	/* see 8240 book for bit definitions */
	343	#elif defined (CONFIG_MPC8245)
	344	#if defined (CONFIG_133MHZ_DRAM)
6d0f6bcf	345	#define CONFIG_SYS_ODCR 0xFE /* configures line driver impedances - 133MHz */
80885a9d	346	#else
6d0f6bcf	347	#define CONFIG_SYS_ODCR 0xDE /* configures line driver impedances - 66MHz */
80885a9d WD	348	#endif
	349	#else
	350	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	351	#endif
	352
6d0f6bcf	353	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
80885a9d WD	354	/* currently accessed page in memory */
	355	/* see 8240 book for details */
	356
	357	/*-----------------------------------------------------------------------
	358	* Block Address Translation (BAT) register settings.
	359	*/
	360	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	361	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	362	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
80885a9d WD	363
80885a9d WD	364	/* stack in DCACHE @ 1GB (no backing mem) */
6d0f6bcf JCPV	365	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	366	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
80885a9d WD	367
80885a9d WD	368	/* PCI memory */
6d0f6bcf JCPV	369	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	370	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
80885a9d WD	371
80885a9d WD	372	/* Flash, config addrs, etc */
6d0f6bcf JCPV	373	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	374	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
80885a9d	375
6d0f6bcf JCPV	376	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	377	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	378	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	379	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	380	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	381	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	382	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	383	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
80885a9d WD	384
	385
	386	/*-----------------------------------------------------------------------
	387	* Cache Configuration
	388	*/
6d0f6bcf	389	#define CONFIG_SYS_CACHELINE_SIZE 32
1bec3d30	390	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	391	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
80885a9d WD	392	#endif
80885a9d WD	393
80885a9d WD	394	/* values according to the manual */
	395	#define CONFIG_DRAM_50MHZ 1
	396	#define CONFIG_SDRAM_50MHZ
	397
	398	#undef NR_8259_INTS
	399	#define NR_8259_INTS 1
	400
	401	/*-----------------------------------------------------------------------
	402	* IDE/ATA stuff
	403	*/
6d0f6bcf JCPV	404	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
6d0f6bcf JCPV	405	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 2 drives per IDE bus */
80885a9d	406
6d0f6bcf JCPV	407	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO /* base address */
	408	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	409	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	410	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	411	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	412	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
80885a9d WD	413
	414	#define CONFIG_ATAPI
	415
	416	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	417	#undef CONFIG_IDE_LED /* no led for ide supported */
	418	#undef CONFIG_IDE_RESET /* reset for ide supported... */
	419	#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
	420
	421	/*-----------------------------------------------------------------------
	422	* DISK Partition support
	423	*/
	424	#define CONFIG_DOS_PARTITION
	425
	426	/*-----------------------------------------------------------------------
	427	* For booting Linux, the board info and command line data
	428	* have to be in the first 8 MB of memory, since this is
	429	* the maximum mapped by the Linux kernel during initialization.
	430	*/
6d0f6bcf	431	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
80885a9d WD	432
80885a9d WD	433	#endif /* __CONFIG_H */