[people/ms/u-boot.git] / include / configs / eb_cpux9k2.h

/*
 * (C) Copyright 2008-2009
 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
 * Jens Scharsig <esw@bus-elektronik.de>
 *
 * Configuation settings for the EB+CPUx9K2 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_EB_CPUx9K2_H_
#define _CONFIG_EB_CPUx9K2_H_

/*--------------------------------------------------------------------------*/

#define CONFIG_AT91RM9200		/* It's an Atmel AT91RM9200 SoC	*/
#define CONFIG_EB_CPUX9K2		/* on an EP+CPUX9K2 Board	*/
#define USE_920T_MMU

#define CONFIG_VERSION_VARIABLE
#define CONFIG_IDENT_STRING	" on EB+CPUx9K2"

#include <asm/hardware.h>	/* needed for port definitions */

#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_EARLY_INIT_F

#define MACH_TYPE_EB_CPUX9K2		1977
#define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2

#define CONFIG_SYS_CACHELINE_SIZE	32
#define CONFIG_SYS_DCACHE_OFF

/*--------------------------------------------------------------------------*/
#ifndef CONFIG_RAMBOOT
#define CONFIG_SYS_TEXT_BASE		0x00000000
#else
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE		0x21800000
#endif
#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
#define CONFIG_STANDALONE_LOAD_ADDR	0x21000000

#define CONFIG_BOOT_RETRY_TIME		30
#define CONFIG_CMDLINE_EDITING

#define CONFIG_SYS_PROMPT	"U-Boot> "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */

/*
 * ARM asynchronous clock
 */

#define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)

#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */

#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL		0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL		0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define CONFIG_SYS_PLLAR_VAL		0x20483E05 /* 179.4048 MHz for PCK */
#define CONFIG_SYS_PLLBR_VAL		0x104C3E0A /* 47.3088 MHz (for USB) */
#define CONFIG_SYS_MCKR_VAL		0x00000202 /* PCK/3 = MCK Clock */

/*
 * Size of malloc() pool
 */

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

/*
 * sdram
 */

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR		0x00204000  /* use internal SRAM */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
					CONFIG_SYS_MALLOC_LEN)

#define CONFIG_SYS_PIOC_ASR_VAL		0xFFFF0000 /* PIOC as D16/D31 */
#define CONFIG_SYS_PIOC_BSR_VAL		0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL		0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL		0x00000002 /* CS1=SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL		0x2188c159 /* set up the SDRAM */
#define CONFIG_SYS_SDRAM		0x20000000 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1		0x20000080 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL		0x00000000 /* value written to SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL		0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1		0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2		0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3		0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL		0x000002E0 /* Write refresh rate */

/*
 * Command line configuration
 */
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_I2C_CMD_TREE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_UBIFS

#define CONFIG_SYS_LONGHELP

/*
 * MTD defines
 */

#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO

#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT	"mtdparts="				\
					"physmap-flash.0:"		\
						"512k(U-Boot),"		\
						"128k(Env),"		\
						"128k(Splash),"		\
						"4M(Kernel),"		\
						"384k(MiniFS),"		\
						"-(FS)"			\
					";"				\
					"atmel_nand:"			\
						"1M(emergency),"	\
						"-(data)"
/*
 * Hardware drivers
 */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_AT91C_PQFP_UHPBUG
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_EFI_PARTITION

#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00300000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"

/*
 * UART/CONSOLE
 */

#define CONFIG_BAUDRATE 115200
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
#define CONFIG_USART_ID		0/* ignored in arm */

/*
 * network
 */

#define CONFIG_NET_RETRY_COUNT		10
#define CONFIG_RESET_PHY_R		1

#define CONFIG_DRIVER_AT91EMAC		1
#define CONFIG_DRIVER_AT91EMAC_QUIET	1
#define CONFIG_SYS_RX_ETH_BUFFER	8
#define CONFIG_MII			1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * I2C-Bus
 */

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0

/* Software  I2C driver configuration */

#define AT91_PIN_SDA			(1<<25)		/* AT91C_PIO_PA25 */
#define AT91_PIN_SCL			(1<<26)		/* AT91C_PIO_PA26 */

#define CONFIG_SYS_I2C_INIT_BOARD

#define I2C_INIT	i2c_init_board();
#define I2C_ACTIVE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
#define I2C_TRISTATE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
#define I2C_READ	((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
#define I2C_SDA(bit)						\
	if (bit)						\
		writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);	\
	else							\
		writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
#define I2C_SCL(bit)						\
	if (bit)						\
		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);	\
	else							\
		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);

#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)

/* I2C-RTC */

#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#endif

/* EEPROM */

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50

/* FLASH organization */

/*  NOR-FLASH */
#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_FLASH_CFI_DRIVER	1

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x01000000  /* 16 megs main flash */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_PROTECTION	1
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	512
#define CONFIG_SYS_FLASH_ERASE_TOUT	6000
#define CONFIG_SYS_FLASH_WRITE_TOUT	2000

/* NAND */

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1

/* Status LED's */

#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1

#define STATUS_LED_BOOT			1
#define STATUS_LED_ACTIVE		0

#define STATUS_LED_BIT			1	/* AT91C_PIO_PD0 green LED */
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE 		STATUS_LED_OFF		/* BLINKING */
#define STATUS_LED_BIT1			2	/* AT91C_PIO_PD1  red LED */
#define STATUS_LED_STATE1		STATUS_LED_ON		/* BLINKING */
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 4)

#define	CONFIG_VIDEO			1

/* Options */

#ifdef CONFIG_VIDEO

#define CONFIG_VIDEO_VCXK			1

#define CONFIG_SPLASH_SCREEN			1

#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	4
#define CONFIG_SYS_VCXK_BASE	0x30000000

#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		(1<<3)
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	piob
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		odr

#define CONFIG_SYS_VCXK_ENABLE_PIN		(1<<5)
#define CONFIG_SYS_VCXK_ENABLE_PORT		piob
#define CONFIG_SYS_VCXK_ENABLE_DDR		oer

#define CONFIG_SYS_VCXK_REQUEST_PIN		(1<<2)
#define CONFIG_SYS_VCXK_REQUEST_PORT		piob
#define CONFIG_SYS_VCXK_REQUEST_DDR		oer

#define CONFIG_SYS_VCXK_INVERT_PIN		(1<<4)
#define CONFIG_SYS_VCXK_INVERT_PORT		piob
#define CONFIG_SYS_VCXK_INVERT_DDR		oer

#define CONFIG_SYS_VCXK_RESET_PIN		(1<<6)
#define CONFIG_SYS_VCXK_RESET_PORT		piob
#define CONFIG_SYS_VCXK_RESET_DDR		oer

#endif	/* CONFIG_VIDEO */

/* Environment */

#define CONFIG_BOOTDELAY		5

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x80000)
#define CONFIG_ENV_SIZE			0x20000 /* sectors are 128K here */

#define CONFIG_BAUDRATE 		115200

#define CONFIG_BOOTCOMMAND		"run nfsboot"

#define CONFIG_NFSBOOTCOMMAND 						\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"run bootargsdefaults;"					\
		"set bootargs $(bootargs) boot=nfs "			\
		";echo $(bootargs)"					\
	";bootm"

#define CONFIG_EXTRA_ENV_SETTINGS 					\
	"displaywidth=256\0"						\
	"displayheight=512\0"						\
	"displaybsteps=1023\0"						\
	"ubootaddr=10000000\0"						\
	"splashimage=100A0000\0"					\
	"kerneladdr=100C0000\0"						\
	"kernelsize=00400000\0"						\
	"rootfsaddr=10520000\0"						\
	"copy_addr=21200000\0"						\
	"rootfssize=00AE0000\0"						\
	"mtdids=" MTDIDS_DEFAULT "\0"					\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"bootargsdefaults=set bootargs "				\
		"console=ttyS0,115200 "					\
		"video=vcxk_fb:xres:${displaywidth},"			\
			"yres:${displayheight},"			\
			"bres:${displaybsteps} "			\
		"mem=62M "						\
		"panic=10 "						\
		"uboot=\\\"${ver}\\\" "					\
		"\0"							\
	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"erase $(kerneladdr) +$(kernelsize);"			\
		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
		"protect on $(kerneladdr) +$(kernelsize)"		\
		"\0"							\
	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
		"dhcp $(copy_addr) rfs;"				\
		"erase $(rootfsaddr) +$(rootfssize);"			\
		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
		"\0"							\
	"update_uboot=protect off 10000000 1007FFFF;"			\
		"dhcp $(copy_addr) u-boot_eb_cpux9k2;"			\
		"erase 10000000 1007FFFF;"				\
		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
		"protect on 10000000 1007FFFF;reset\0"			\
	"update_splash=protect off $(splashimage) +20000;"		\
		"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"		\
		"erase $(splashimage) +20000;"				\
		"cp.b $(fileaddr) $(splashimage) $(filesize);"		\
		"protect on $(splashimage) +20000;reset\0"		\
	"emergency=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(kerneladdr)\0"				\
	"netemergency=run bootargsdefaults;"				\
		"dhcp $(copy_addr) uImage_cpux9k2;"			\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(copy_addr)\0"					\
	"norboot=run bootargsdefaults;"					\
		"set bootargs $(bootargs) root=initramfs boot=local "	\
		";bootm $(kerneladdr)\0"				\
	"nandboot=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=nand "	\
		";bootm $(kerneladdr)\0"				\
	" "

/*--------------------------------------------------------------------------*/

#endif

/* EOF */
Commit	Line	Data
77e7273c JS	1	/*
	2	* (C) Copyright 2008-2009
	3	* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
	4	* Jens Scharsig <esw@bus-elektronik.de>
	5	*
	6	* Configuation settings for the EB+CPUx9K2 board.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
77e7273c JS	9	*/
	10
	11	#ifndef _CONFIG_EB_CPUx9K2_H_
	12	#define _CONFIG_EB_CPUx9K2_H_
	13
	14	/--------------------------------------------------------------------------/
	15
80733994 JS	16	#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
	17	#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
	18	#define USE_920T_MMU
77e7273c	19
80733994	20	#define CONFIG_VERSION_VARIABLE
77e7273c JS	21	#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
77e7273c JS	22
6a372e94	23	#include <asm/hardware.h> /* needed for port definitions */
77e7273c JS	24
77e7273c JS	25	#define CONFIG_MISC_INIT_R
5a05cb73	26	#define CONFIG_BOARD_EARLY_INIT_F
77e7273c	27
2026a119 JS	28	#define MACH_TYPE_EB_CPUX9K2 1977
2026a119 JS	29	#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
cc69cc00 JSBE	30
	31	#define CONFIG_SYS_CACHELINE_SIZE 32
	32	#define CONFIG_SYS_DCACHE_OFF
	33
77e7273c	34	/--------------------------------------------------------------------------/
503e159b JS	35	#ifndef CONFIG_RAMBOOT
	36	#define CONFIG_SYS_TEXT_BASE 0x00000000
	37	#else
	38	#define CONFIG_SKIP_LOWLEVEL_INIT
f89a6ee3	39	#define CONFIG_SYS_TEXT_BASE 0x21800000
503e159b	40	#endif
77e7273c	41	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
bc695898	42	#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
77e7273c	43
77e7273c JS	44	#define CONFIG_BOOT_RETRY_TIME 30
	45	#define CONFIG_CMDLINE_EDITING
	46
	47	#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
	48	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	49	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	50	#define CONFIG_SYS_PBSIZE \
	51	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	52
77e7273c JS	53	/*
	54	* ARM asynchronous clock
	55	*/
	56
	57	#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
	58	#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
77e7273c JS	59	#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
77e7273c JS	60
6a372e94	61	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
77e7273c JS	62
	63	#define CONFIG_CMDLINE_TAG 1
	64	#define CONFIG_SETUP_MEMORY_TAGS 1
	65	#define CONFIG_INITRD_TAG 1
	66
	67	#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
	68	/* flash */
	69	#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
	70	#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	71
	72	/* clocks */
	73	#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
	74	#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
	75	#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
	76
	77	/*
	78	* Size of malloc() pool
	79	*/
	80
db824479	81	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
77e7273c JS	82
	83	/*
	84	* sdram
	85	*/
	86
	87	#define CONFIG_NR_DRAM_BANKS 1
77e7273c	88
cebcf7da JS	89	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	90	#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	91	#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
	92
	93	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
77e7273c	94	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
cebcf7da	95	CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
77e7273c JS	96	CONFIG_SYS_MALLOC_LEN)
	97
	98	#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
	99	#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
	100	#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
	101	#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	102	#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
	103	#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
	104	#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
	105	#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
	106	#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
	107	#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
	108	#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	109	#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	110	#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
	111
	112	/*
	113	* Command line configuration
	114	*/
77e7273c JS	115	#define CONFIG_CMD_BMP
	116	#define CONFIG_CMD_DATE
	117	#define CONFIG_CMD_DHCP
	118	#define CONFIG_CMD_I2C
77e7273c JS	119	#define CONFIG_CMD_MII
	120	#define CONFIG_CMD_NAND
	121	#define CONFIG_CMD_PING
77e7273c	122	#define CONFIG_I2C_CMD_TREE
0d62032e JS	123	#define CONFIG_CMD_USB
0d62032e JS	124	#define CONFIG_CMD_FAT
bc695898 JSBE	125	#define CONFIG_CMD_UBI
	126	#define CONFIG_CMD_MTDPARTS
	127	#define CONFIG_CMD_UBIFS
f89a6ee3	128
77e7273c JS	129	#define CONFIG_SYS_LONGHELP
	130
	131	/*
bc695898	132	* MTD defines
77e7273c JS	133	*/
77e7273c JS	134
bc695898 JSBE	135	#define CONFIG_FLASH_CFI_MTD
	136	#define CONFIG_MTD_DEVICE
	137	#define CONFIG_MTD_PARTITIONS
	138	#define CONFIG_RBTREE
	139	#define CONFIG_LZO
77e7273c	140
bc695898	141	#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
77e7273c	142	#define MTDPARTS_DEFAULT "mtdparts=" \
bc695898 JSBE	143	"physmap-flash.0:" \
	144	"512k(U-Boot)," \
	145	"128k(Env)," \
	146	"128k(Splash)," \
	147	"4M(Kernel)," \
	148	"384k(MiniFS)," \
	149	"-(FS)" \
77e7273c	150	";" \
bc695898 JSBE	151	"atmel_nand:" \
	152	"1M(emergency)," \
	153	"-(data)"
77e7273c JS	154	/*
	155	* Hardware drivers
	156	*/
0d62032e	157	#define CONFIG_USB_ATMEL
dcd2f1a0	158	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
0d62032e JS	159	#define CONFIG_USB_OHCI_NEW
	160	#define CONFIG_AT91C_PQFP_UHPBUG
	161	#define CONFIG_USB_STORAGE
	162	#define CONFIG_DOS_PARTITION
	163	#define CONFIG_ISO_PARTITION
	164	#define CONFIG_EFI_PARTITION
	165
	166	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
	167	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	168	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
	169	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
77e7273c JS	170
	171	/*
	172	* UART/CONSOLE
	173	*/
	174
77e7273c	175	#define CONFIG_BAUDRATE 115200
5a05cb73 AB	176	#define CONFIG_ATMEL_USART
	177	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	178	#define CONFIG_USART_ID 0/* ignored in arm */
77e7273c JS	179
	180	/*
	181	* network
	182	*/
77e7273c JS	183
	184	#define CONFIG_NET_RETRY_COUNT 10
	185	#define CONFIG_RESET_PHY_R 1
	186
	187	#define CONFIG_DRIVER_AT91EMAC 1
	188	#define CONFIG_DRIVER_AT91EMAC_QUIET 1
	189	#define CONFIG_SYS_RX_ETH_BUFFER 8
	190	#define CONFIG_MII 1
	191
	192	/*
	193	* BOOTP options
	194	*/
	195	#define CONFIG_BOOTP_BOOTFILESIZE
	196	#define CONFIG_BOOTP_BOOTPATH
	197	#define CONFIG_BOOTP_GATEWAY
	198	#define CONFIG_BOOTP_HOSTNAME
	199
	200	/*
	201	* I2C-Bus
	202	*/
	203
ea818dbb HS	204	#define CONFIG_SYS_I2C
	205	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	206	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	207	#define CONFIG_SYS_I2C_SOFT_SLAVE 0
77e7273c JS	208
	209	/* Software I2C driver configuration */
	210
	211	#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
	212	#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
	213
	214	#define CONFIG_SYS_I2C_INIT_BOARD
	215
	216	#define I2C_INIT i2c_init_board();
80733994 JS	217	#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
	218	#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
	219	#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
77e7273c JS	220	#define I2C_SDA(bit) \
77e7273c JS	221	if (bit) \
80733994	222	writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
77e7273c	223	else \
80733994	224	writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
77e7273c JS	225	#define I2C_SCL(bit) \
77e7273c JS	226	if (bit) \
80733994	227	writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
77e7273c	228	else \
80733994	229	writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
77e7273c	230
ea818dbb	231	#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
77e7273c JS	232
	233	/* I2C-RTC */
	234
	235	#ifdef CONFIG_CMD_DATE
	236	#define CONFIG_RTC_DS1338
	237	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	238	#endif
	239
	240	/* EEPROM */
	241
	242	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	243	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	244
	245	/* FLASH organization */
	246
	247	/* NOR-FLASH */
cebcf7da	248	#define CONFIG_FLASH_SHOW_PROGRESS 45
77e7273c JS	249
	250	#define CONFIG_FLASH_CFI_DRIVER 1
	251
	252	#define PHYS_FLASH_1 0x10000000
	253	#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
	254	#define CONFIG_SYS_FLASH_CFI 1
	255	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	256
	257	#define CONFIG_SYS_FLASH_PROTECTION 1
	258	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	259	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	260	#define CONFIG_SYS_MAX_FLASH_SECT 512
	261	#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
	262	#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
	263
	264	/* NAND */
	265
77e7273c JS	266	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	267	#define CONFIG_SYS_NAND_BASE 0x40000000
	268	#define CONFIG_SYS_NAND_DBW_8 1
	269
77e7273c JS	270	/* Status LED's */
	271
	272	#define CONFIG_STATUS_LED 1
	273	#define CONFIG_BOARD_SPECIFIC_LED 1
	274
	275	#define STATUS_LED_BOOT 1
	276	#define STATUS_LED_ACTIVE 0
	277
	278	#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
	279	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	280	#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
	281	#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
	282	#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
	283	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
	284
	285	#define CONFIG_VIDEO 1
	286
	287	/* Options */
	288
	289	#ifdef CONFIG_VIDEO
	290
	291	#define CONFIG_VIDEO_VCXK 1
	292
	293	#define CONFIG_SPLASH_SCREEN 1
	294
	295	#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
	296	#define CONFIG_SYS_VCXK_BASE 0x30000000
	297
	298	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
	299	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
	300	#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
	301
	302	#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
	303	#define CONFIG_SYS_VCXK_ENABLE_PORT piob
	304	#define CONFIG_SYS_VCXK_ENABLE_DDR oer
	305
	306	#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
	307	#define CONFIG_SYS_VCXK_REQUEST_PORT piob
	308	#define CONFIG_SYS_VCXK_REQUEST_DDR oer
	309
	310	#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
	311	#define CONFIG_SYS_VCXK_INVERT_PORT piob
	312	#define CONFIG_SYS_VCXK_INVERT_DDR oer
	313
	314	#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
	315	#define CONFIG_SYS_VCXK_RESET_PORT piob
	316	#define CONFIG_SYS_VCXK_RESET_DDR oer
	317
	318	#endif /* CONFIG_VIDEO */
	319
	320	/* Environment */
	321
	322	#define CONFIG_BOOTDELAY 5
	323
	324	#define CONFIG_ENV_IS_IN_FLASH 1
bc695898	325	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
77e7273c JS	326	#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
	327
	328	#define CONFIG_BAUDRATE 115200
	329
	330	#define CONFIG_BOOTCOMMAND "run nfsboot"
	331
	332	#define CONFIG_NFSBOOTCOMMAND \
	333	"dhcp $(copy_addr) uImage_cpux9k2;" \
	334	"run bootargsdefaults;" \
	335	"set bootargs $(bootargs) boot=nfs " \
	336	";echo $(bootargs)" \
	337	";bootm"
	338
	339	#define CONFIG_EXTRA_ENV_SETTINGS \
	340	"displaywidth=256\0" \
	341	"displayheight=512\0" \
	342	"displaybsteps=1023\0" \
	343	"ubootaddr=10000000\0" \
bc695898 JSBE	344	"splashimage=100A0000\0" \
bc695898 JSBE	345	"kerneladdr=100C0000\0" \
77e7273c	346	"kernelsize=00400000\0" \
bc695898	347	"rootfsaddr=10520000\0" \
77e7273c	348	"copy_addr=21200000\0" \
bc695898 JSBE	349	"rootfssize=00AE0000\0" \
	350	"mtdids=" MTDIDS_DEFAULT "\0" \
	351	"mtdparts=" MTDPARTS_DEFAULT "\0" \
77e7273c JS	352	"bootargsdefaults=set bootargs " \
	353	"console=ttyS0,115200 " \
	354	"video=vcxk_fb:xres:${displaywidth}," \
	355	"yres:${displayheight}," \
	356	"bres:${displaybsteps} " \
	357	"mem=62M " \
	358	"panic=10 " \
	359	"uboot=\\\"${ver}\\\" " \
	360	"\0" \
	361	"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
	362	"dhcp $(copy_addr) uImage_cpux9k2;" \
	363	"erase $(kerneladdr) +$(kernelsize);" \
	364	"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
	365	"protect on $(kerneladdr) +$(kernelsize)" \
	366	"\0" \
	367	"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
	368	"dhcp $(copy_addr) rfs;" \
	369	"erase $(rootfsaddr) +$(rootfssize);" \
	370	"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
	371	"\0" \
bc695898	372	"update_uboot=protect off 10000000 1007FFFF;" \
77e7273c	373	"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
bc695898	374	"erase 10000000 1007FFFF;" \
77e7273c	375	"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
bc695898	376	"protect on 10000000 1007FFFF;reset\0" \
77e7273c JS	377	"update_splash=protect off $(splashimage) +20000;" \
	378	"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
	379	"erase $(splashimage) +20000;" \
bc695898	380	"cp.b $(fileaddr) $(splashimage) $(filesize);" \
77e7273c JS	381	"protect on $(splashimage) +20000;reset\0" \
	382	"emergency=run bootargsdefaults;" \
	383	"set bootargs $(bootargs) root=initramfs boot=emergency " \
	384	";bootm $(kerneladdr)\0" \
	385	"netemergency=run bootargsdefaults;" \
	386	"dhcp $(copy_addr) uImage_cpux9k2;" \
	387	"set bootargs $(bootargs) root=initramfs boot=emergency " \
	388	";bootm $(copy_addr)\0" \
	389	"norboot=run bootargsdefaults;" \
	390	"set bootargs $(bootargs) root=initramfs boot=local " \
	391	";bootm $(kerneladdr)\0" \
	392	"nandboot=run bootargsdefaults;" \
	393	"set bootargs $(bootargs) root=initramfs boot=nand " \
	394	";bootm $(kerneladdr)\0" \
77e7273c JS	395	" "
	396
	397	/--------------------------------------------------------------------------/
	398
	399	#endif
	400
	401	/* EOF */