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ce9c227c | 1 | /* |
57b4bce9 | 2 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
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3 | * |
4 | * Based on original Kirkwood support which is | |
5 | * (C) Copyright 2009 | |
6 | * Marvell Semiconductor <www.marvell.com> | |
7 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
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10 | */ |
11 | ||
12 | #ifndef _CONFIG_EDMINIV2_H | |
13 | #define _CONFIG_EDMINIV2_H | |
14 | ||
15 | /* | |
16 | * Version number information | |
17 | */ | |
18 | ||
19 | #define CONFIG_IDENT_STRING " EDMiniV2" | |
20 | ||
21 | /* | |
22 | * High Level Configuration Options (easy to change) | |
23 | */ | |
24 | ||
25 | #define CONFIG_MARVELL 1 | |
ce9c227c | 26 | #define CONFIG_FEROCEON 1 /* CPU Core subversion */ |
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27 | #define CONFIG_88F5182 1 /* SOC Name */ |
28 | #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ | |
29 | ||
5ff8b354 | 30 | #include <asm/arch/orion5x.h> |
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31 | /* |
32 | * CLKs configurations | |
33 | */ | |
34 | ||
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35 | /* |
36 | * Board-specific values for Orion5x MPP low level init: | |
37 | * - MPPs 12 to 15 are SATA LEDs (mode 5) | |
38 | * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for | |
39 | * MPP16 to MPP19, mode 0 for others | |
40 | */ | |
41 | ||
42 | #define ORION5X_MPP0_7 0x00000003 | |
43 | #define ORION5X_MPP8_15 0x55550000 | |
ecaf3af2 | 44 | #define ORION5X_MPP16_23 0x00005555 |
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45 | |
46 | /* | |
47 | * Board-specific values for Orion5x GPIO low level init: | |
48 | * - GPIO3 is input (RTC interrupt) | |
49 | * - GPIO16 is Power LED control (0 = on, 1 = off) | |
50 | * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) | |
51 | * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) | |
491f6c2f AA |
52 | * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) |
53 | * - GPIO22 is SATA disk power status () | |
54 | * - GPIO23 is supply status for SATA disk () | |
55 | * - GPIO24 is supply control for board (write 1 to power off) | |
56 | * Last GPIO is 25, further bits are supposed to be 0. | |
ce9c227c | 57 | * Enable mask has ones for INPUT, 0 for OUTPUT. |
491f6c2f | 58 | * Default is LED ON, board ON :) |
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59 | */ |
60 | ||
491f6c2f AA |
61 | #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca |
62 | #define ORION5X_GPIO_OUT_VALUE 0x00000000 | |
63 | #define ORION5X_GPIO_IN_POLARITY 0x000000d0 | |
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64 | |
65 | /* | |
66 | * NS16550 Configuration | |
67 | */ | |
68 | ||
69 | #define CONFIG_SYS_NS16550 | |
70 | #define CONFIG_SYS_NS16550_SERIAL | |
71 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
72 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK | |
73 | #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE | |
74 | ||
75 | /* | |
76 | * Serial Port configuration | |
77 | * The following definitions let you select what serial you want to use | |
78 | * for your console driver. | |
79 | */ | |
80 | ||
81 | #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ | |
82 | #define CONFIG_BAUDRATE 115200 | |
83 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
84 | { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } | |
85 | ||
86 | /* | |
87 | * FLASH configuration | |
88 | */ | |
89 | ||
90 | #define CONFIG_SYS_FLASH_CFI | |
91 | #define CONFIG_FLASH_CFI_DRIVER | |
92 | #define CONFIG_FLASH_CFI_LEGACY | |
93 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
94 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ | |
95 | #define CONFIG_SYS_FLASH_BASE 0xfff80000 | |
96 | #define CONFIG_SYS_FLASH_SECTSZ \ | |
97 | {16384, 8192, 8192, 32768, \ | |
98 | 65536, 65536, 65536, 65536, 65536, 65536, 65536} | |
99 | ||
100 | /* auto boot */ | |
101 | #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ | |
102 | ||
103 | /* | |
104 | * For booting Linux, the board info and command line data | |
105 | * have to be in the first 8 MB of memory, since this is | |
106 | * the maximum mapped by the Linux kernel during initialization. | |
107 | */ | |
108 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
109 | #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ | |
110 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ | |
111 | ||
112 | #define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ | |
113 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ | |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ | |
115 | +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ | |
116 | /* | |
117 | * Commands configuration - using default command set for now | |
118 | */ | |
119 | #include <config_cmd_default.h> | |
ecaf3af2 | 120 | #define CONFIG_CMD_IDE |
c2ca44c2 | 121 | #define CONFIG_CMD_I2C |
81a6c009 | 122 | #define CONFIG_CMD_USB |
ab9164d0 | 123 | |
ce9c227c | 124 | /* |
ab9164d0 | 125 | * Network |
ce9c227c | 126 | */ |
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127 | |
128 | #ifdef CONFIG_CMD_NET | |
129 | #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ | |
130 | #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ | |
131 | #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ | |
132 | #define CONFIG_PHY_BASE_ADR 0x8 | |
133 | #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ | |
134 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
ab9164d0 AA |
135 | #define CONFIG_MII /* expose smi ove miiphy interface */ |
136 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ | |
137 | #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ | |
138 | #endif | |
ce9c227c | 139 | |
ecaf3af2 AA |
140 | /* |
141 | * IDE | |
142 | */ | |
143 | #ifdef CONFIG_CMD_IDE | |
144 | #define __io | |
145 | #define CONFIG_IDE_PREINIT | |
146 | #define CONFIG_DOS_PARTITION | |
147 | #define CONFIG_CMD_EXT2 | |
148 | /* ED Mini V has an IDE-compatible SATA connector for port 1 */ | |
149 | #define CONFIG_MVSATA_IDE | |
150 | #define CONFIG_MVSATA_IDE_USE_PORT1 | |
151 | /* Needs byte-swapping for ATA data register */ | |
152 | #define CONFIG_IDE_SWAP_IO | |
153 | /* Data, registers and alternate blocks are at the same offset */ | |
154 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) | |
155 | #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) | |
156 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) | |
157 | /* Each 8-bit ATA register is aligned to a 4-bytes address */ | |
158 | #define CONFIG_SYS_ATA_STRIDE 4 | |
159 | /* Controller supports 48-bits LBA addressing */ | |
160 | #define CONFIG_LBA48 | |
161 | /* A single bus, a single device */ | |
162 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
163 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
164 | /* ATA registers base is at SATA controller base */ | |
165 | #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE | |
166 | /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ | |
167 | #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET | |
168 | /* end of IDE defines */ | |
169 | #endif /* CMD_IDE */ | |
170 | ||
81a6c009 AA |
171 | /* |
172 | * Common USB/EHCI configuration | |
173 | */ | |
174 | #ifdef CONFIG_CMD_USB | |
175 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
176 | #define CONFIG_USB_EHCI_MARVELL | |
177 | #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE | |
178 | #define CONFIG_USB_STORAGE | |
179 | #define CONFIG_DOS_PARTITION | |
180 | #define CONFIG_ISO_PARTITION | |
181 | #define CONFIG_SUPPORT_VFAT | |
182 | #endif /* CONFIG_CMD_USB */ | |
183 | ||
c2ca44c2 AA |
184 | /* |
185 | * I2C related stuff | |
186 | */ | |
187 | #ifdef CONFIG_CMD_I2C | |
0db2bbdc HG |
188 | #define CONFIG_SYS_I2C |
189 | #define CONFIG_SYS_I2C_MVTWSI | |
c2ca44c2 AA |
190 | #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE |
191 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
192 | #define CONFIG_SYS_I2C_SPEED 100000 | |
193 | #endif | |
194 | ||
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195 | /* |
196 | * Environment variables configurations | |
197 | */ | |
198 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
199 | #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ | |
200 | #define CONFIG_ENV_SIZE 0x2000 | |
201 | #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ | |
202 | ||
203 | /* | |
204 | * Size of malloc() pool | |
205 | */ | |
84fb04b6 | 206 | #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ |
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207 | |
208 | /* | |
209 | * Other required minimal configurations | |
210 | */ | |
211 | #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ | |
212 | #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ | |
213 | #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ | |
214 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ | |
215 | #define CONFIG_NR_DRAM_BANKS 1 | |
216 | ||
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217 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 |
218 | #define CONFIG_SYS_MEMTEST_START 0x00400000 | |
219 | #define CONFIG_SYS_MEMTEST_END 0x007fffff | |
220 | #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 | |
221 | #define CONFIG_SYS_MAXARGS 16 | |
222 | ||
a203a7c8 AA |
223 | /* Use the HUSH parser */ |
224 | #define CONFIG_SYS_HUSH_PARSER | |
a203a7c8 AA |
225 | |
226 | /* Enable command line editing */ | |
227 | #define CONFIG_CMDLINE_EDITING | |
228 | ||
229 | /* provide extensive help */ | |
230 | #define CONFIG_SYS_LONGHELP | |
231 | ||
0693923c AA |
232 | /* additions for new relocation code, must be added to all boards */ |
233 | #define CONFIG_SYS_SDRAM_BASE 0 | |
234 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
25ddd1fb | 235 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) |
0693923c | 236 | |
ce9c227c | 237 | #endif /* _CONFIG_EDMINIV2_H */ |