[people/ms/u-boot.git] / include / configs / edminiv2.h

/*
 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
 *
 * Based on original Kirkwood support which is
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_EDMINIV2_H
#define _CONFIG_EDMINIV2_H

/*
 * SPL
 */

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0xffff0000
#define CONFIG_SPL_MAX_SIZE		0x0000fff0
#define CONFIG_SPL_STACK		0x00020000
#define CONFIG_SPL_BSS_START_ADDR	0x00020000
#define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
#define CONFIG_SYS_SPL_MALLOC_START	0x00040000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/orion5x/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_UBOOT_BASE		0xfff90000
#define CONFIG_SYS_UBOOT_START		0x00800000
#define CONFIG_SYS_TEXT_BASE 		0x00800000

/*
 * High Level Configuration Options (easy to change)
 */

#define CONFIG_MARVELL		1
#define CONFIG_FEROCEON		1	/* CPU Core subversion */
#define CONFIG_88F5182		1	/* SOC Name */
#define CONFIG_MACH_EDMINIV2	1	/* Machine type */

#include <asm/arch/orion5x.h>
/*
 * CLKs configurations
 */

/*
 * Board-specific values for Orion5x MPP low level init:
 * - MPPs 12 to 15 are SATA LEDs (mode 5)
 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
 *   MPP16 to MPP19, mode 0 for others
 */

#define ORION5X_MPP0_7		0x00000003
#define ORION5X_MPP8_15		0x55550000
#define ORION5X_MPP16_23	0x00005555

/*
 * Board-specific values for Orion5x GPIO low level init:
 * - GPIO3 is input (RTC interrupt)
 * - GPIO16 is Power LED control (0 = on, 1 = off)
 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
 * - GPIO22 is SATA disk power status ()
 * - GPIO23 is supply status for SATA disk ()
 * - GPIO24 is supply control for board (write 1 to power off)
 * Last GPIO is 25, further bits are supposed to be 0.
 * Enable mask has ones for INPUT, 0 for OUTPUT.
 * Default is LED ON, board ON :)
 */

#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
#define ORION5X_GPIO_OUT_VALUE		0x00000000
#define ORION5X_GPIO_IN_POLARITY	0x000000d0

/*
 * NS16550 Configuration
 */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE

/*
 * Serial Port configuration
 * The following definitions let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }

/*
 * FLASH configuration
 */

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE		0xfff80000

/* auto boot */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */

#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
/*
 * Commands configuration
 */
#define CONFIG_CMD_IDE

/*
 * Network
 */

#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE				/* Enable Marvell GbE Driver */
#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
#define CONFIG_PHY_BASE_ADR	0x8
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define	CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#endif

/*
 * IDE
 */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
#define CONFIG_MVSATA_IDE
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */

/*
 * Common USB/EHCI configuration
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI		/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MARVELL
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */

/*
 * I2C related stuff
 */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

/*
 *  Environment variables configurations
 */
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	(1024 * 256) /* 256kB for malloc() */

/*
 * Other required minimal configurations
 */
#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_LOAD_ADDR		0x00800000
#define CONFIG_SYS_MEMTEST_START	0x00400000
#define CONFIG_SYS_MEMTEST_END		0x007fffff
#define CONFIG_SYS_RESET_ADDRESS	0xffff0000
#define CONFIG_SYS_MAXARGS		16

/* Enable command line editing */
#define CONFIG_CMDLINE_EDITING

/* provide extensive help */
#define CONFIG_SYS_LONGHELP

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0
#define CONFIG_SYS_INIT_SP_ADDR	\
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#endif /* _CONFIG_EDMINIV2_H */
Commit	Line	Data
ce9c227c	1	/*
57b4bce9	2	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
ce9c227c AA	3	*
	4	* Based on original Kirkwood support which is
	5	* (C) Copyright 2009
	6	* Marvell Semiconductor <www.marvell.com>
	7	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
ce9c227c AA	10	*/
	11
	12	#ifndef _CONFIG_EDMINIV2_H
	13	#define _CONFIG_EDMINIV2_H
	14
9608e7de AA	15	/*
	16	* SPL
	17	*/
	18
	19	#define CONFIG_SPL_FRAMEWORK
9608e7de AA	20	#define CONFIG_SPL_TEXT_BASE 0xffff0000
	21	#define CONFIG_SPL_MAX_SIZE 0x0000fff0
	22	#define CONFIG_SPL_STACK 0x00020000
	23	#define CONFIG_SPL_BSS_START_ADDR 0x00020000
	24	#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
	25	#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
	26	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
	27	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
	28	#define CONFIG_SPL_BOARD_INIT
	29	#define CONFIG_SYS_UBOOT_BASE 0xfff90000
	30	#define CONFIG_SYS_UBOOT_START 0x00800000
	31	#define CONFIG_SYS_TEXT_BASE 0x00800000
	32
ce9c227c AA	33	/*
	34	* High Level Configuration Options (easy to change)
	35	*/
	36
	37	#define CONFIG_MARVELL 1
ce9c227c	38	#define CONFIG_FEROCEON 1 /* CPU Core subversion */
ce9c227c AA	39	#define CONFIG_88F5182 1 /* SOC Name */
	40	#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
	41
5ff8b354	42	#include <asm/arch/orion5x.h>
ce9c227c AA	43	/*
	44	* CLKs configurations
	45	*/
	46
ce9c227c AA	47	/*
	48	* Board-specific values for Orion5x MPP low level init:
	49	* - MPPs 12 to 15 are SATA LEDs (mode 5)
	50	* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
	51	* MPP16 to MPP19, mode 0 for others
	52	*/
	53
	54	#define ORION5X_MPP0_7 0x00000003
	55	#define ORION5X_MPP8_15 0x55550000
ecaf3af2	56	#define ORION5X_MPP16_23 0x00005555
ce9c227c AA	57
	58	/*
	59	* Board-specific values for Orion5x GPIO low level init:
	60	* - GPIO3 is input (RTC interrupt)
	61	* - GPIO16 is Power LED control (0 = on, 1 = off)
	62	* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
	63	* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
491f6c2f AA	64	* - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
	65	* - GPIO22 is SATA disk power status ()
	66	* - GPIO23 is supply status for SATA disk ()
	67	* - GPIO24 is supply control for board (write 1 to power off)
	68	* Last GPIO is 25, further bits are supposed to be 0.
ce9c227c	69	* Enable mask has ones for INPUT, 0 for OUTPUT.
491f6c2f	70	* Default is LED ON, board ON :)
ce9c227c AA	71	*/
ce9c227c AA	72
491f6c2f AA	73	#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
	74	#define ORION5X_GPIO_OUT_VALUE 0x00000000
	75	#define ORION5X_GPIO_IN_POLARITY 0x000000d0
ce9c227c AA	76
	77	/*
	78	* NS16550 Configuration
	79	*/
	80
ce9c227c AA	81	#define CONFIG_SYS_NS16550_SERIAL
	82	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	83	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
	84	#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
	85
	86	/*
	87	* Serial Port configuration
	88	* The following definitions let you select what serial you want to use
	89	* for your console driver.
	90	*/
	91
	92	#define CONFIG_CONS_INDEX 1 /Console on UART0 /
ce9c227c AA	93	#define CONFIG_SYS_BAUDRATE_TABLE \
	94	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
	95
	96	/*
	97	* FLASH configuration
	98	*/
	99
	100	#define CONFIG_SYS_FLASH_CFI
	101	#define CONFIG_FLASH_CFI_DRIVER
ce9c227c AA	102	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	103	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
	104	#define CONFIG_SYS_FLASH_BASE 0xfff80000
ce9c227c AA	105
ce9c227c AA	106	/* auto boot */
ce9c227c AA	107
	108	/*
	109	* For booting Linux, the board info and command line data
	110	* have to be in the first 8 MB of memory, since this is
	111	* the maximum mapped by the Linux kernel during initialization.
	112	*/
	113	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	114	#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
	115	#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
	116
ce9c227c AA	117	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
	118	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	119	+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
	120	/*
ef0f2f57	121	* Commands configuration
ce9c227c	122	*/
ecaf3af2	123	#define CONFIG_CMD_IDE
ab9164d0	124
ce9c227c	125	/*
ab9164d0	126	* Network
ce9c227c	127	*/
ab9164d0 AA	128
	129	#ifdef CONFIG_CMD_NET
	130	#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
	131	#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
	132	#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
	133	#define CONFIG_PHY_BASE_ADR 0x8
	134	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
	135	#define CONFIG_NETCONSOLE /* include NetConsole support */
ab9164d0 AA	136	#define CONFIG_MII /* expose smi ove miiphy interface */
	137	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
	138	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	139	#endif
ce9c227c	140
ecaf3af2 AA	141	/*
	142	* IDE
	143	*/
	144	#ifdef CONFIG_CMD_IDE
	145	#define __io
	146	#define CONFIG_IDE_PREINIT
ecaf3af2 AA	147	/* ED Mini V has an IDE-compatible SATA connector for port 1 */
	148	#define CONFIG_MVSATA_IDE
	149	#define CONFIG_MVSATA_IDE_USE_PORT1
	150	/* Needs byte-swapping for ATA data register */
	151	#define CONFIG_IDE_SWAP_IO
	152	/* Data, registers and alternate blocks are at the same offset */
	153	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
	154	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
	155	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
	156	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	157	#define CONFIG_SYS_ATA_STRIDE 4
	158	/* Controller supports 48-bits LBA addressing */
	159	#define CONFIG_LBA48
	160	/* A single bus, a single device */
	161	#define CONFIG_SYS_IDE_MAXBUS 1
	162	#define CONFIG_SYS_IDE_MAXDEVICE 1
	163	/* ATA registers base is at SATA controller base */
	164	#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
	165	/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
	166	#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
	167	/* end of IDE defines */
	168	#endif /* CMD_IDE */
	169
81a6c009 AA	170	/*
	171	* Common USB/EHCI configuration
	172	*/
	173	#ifdef CONFIG_CMD_USB
	174	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	175	#define CONFIG_USB_EHCI_MARVELL
	176	#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
81a6c009 AA	177	#define CONFIG_SUPPORT_VFAT
	178	#endif /* CONFIG_CMD_USB */
	179
c2ca44c2 AA	180	/*
	181	* I2C related stuff
	182	*/
	183	#ifdef CONFIG_CMD_I2C
0db2bbdc HG	184	#define CONFIG_SYS_I2C
0db2bbdc HG	185	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	186	#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
c2ca44c2 AA	187	#define CONFIG_SYS_I2C_SLAVE 0x0
	188	#define CONFIG_SYS_I2C_SPEED 100000
	189	#endif
	190
ce9c227c AA	191	/*
	192	* Environment variables configurations
	193	*/
	194	#define CONFIG_ENV_IS_IN_FLASH 1
	195	#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
	196	#define CONFIG_ENV_SIZE 0x2000
	197	#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
	198
	199	/*
	200	* Size of malloc() pool
	201	*/
84fb04b6	202	#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
ce9c227c AA	203
	204	/*
	205	* Other required minimal configurations
	206	*/
ce9c227c	207	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
ce9c227c AA	208	#define CONFIG_NR_DRAM_BANKS 1
ce9c227c AA	209
ce9c227c AA	210	#define CONFIG_SYS_LOAD_ADDR 0x00800000
	211	#define CONFIG_SYS_MEMTEST_START 0x00400000
	212	#define CONFIG_SYS_MEMTEST_END 0x007fffff
	213	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
	214	#define CONFIG_SYS_MAXARGS 16
	215
a203a7c8 AA	216	/* Enable command line editing */
	217	#define CONFIG_CMDLINE_EDITING
	218
	219	/* provide extensive help */
	220	#define CONFIG_SYS_LONGHELP
	221
0693923c AA	222	/* additions for new relocation code, must be added to all boards */
	223	#define CONFIG_SYS_SDRAM_BASE 0
	224	#define CONFIG_SYS_INIT_SP_ADDR \
25ddd1fb	225	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
0693923c	226
ce9c227c	227	#endif /* _CONFIG_EDMINIV2_H */