projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5b1d7137 WD |
1 | /* |
| 2 | * (C) Copyright 2002 | |
| 3 | * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG | |
| 4 | * | |
| 5 | * This file is based on similar values for other boards found in other | |
| 6 | * U-Boot config files, and some that I found in the EP8260 manual. | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | /* | |
| 28 | * board/config.h - configuration options, board specific | |
| 29 | * | |
| 30 | * Note: my board is a "SBC 8260 H, V.1.1" | |
| 31 | * - 64M 60x Bus SDRAM | |
| 32 | * - 32M Local Bus SDRAM | |
| 33 | * - 16M Flash (4 x AM29DL323DB90WDI) | |
| 34 | * - 128k NVRAM with RTC | |
| 35 | */ | |
| 36 | ||
| 37 | #ifndef __CONFIG_H | |
| 38 | #define __CONFIG_H | |
| 39 | ||
| 40 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
| 41 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
| 42 | ||
| 43 | /*----------------------------------------------------------------------- | |
| 44 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
| 45 | *----------------------------------------------------------------------- | |
| 46 | * What should MODCK_H be? It is dependent on the oscillator | |
| 47 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
| 48 | * Here are some example values (all frequencies are in MHz): | |
| 49 | * | |
| 50 | * MODCK_H MODCK[1-3] Osc CPM Core | |
| 51 | * ------- ---------- --- --- ---- | |
| 52 | * 0x2 0x2 33 133 133 | |
| 53 | * 0x2 0x3 33 133 166 | |
| 54 | * 0x2 0x4 33 133 200 | |
| 55 | * 0x2 0x5 33 133 233 | |
| 56 | * 0x2 0x6 33 133 266 | |
| 57 | * | |
| 58 | * 0x5 0x5 66 133 133 | |
| 59 | * 0x5 0x6 66 133 166 | |
| 60 | * 0x5 0x7 66 133 200 * | |
| 61 | * 0x6 0x0 66 133 233 | |
| 62 | * 0x6 0x1 66 133 266 | |
| 63 | * 0x6 0x2 66 133 300 | |
| 64 | */ | |
| 65 | #define CFG_SBC_MODCK_H 0x05 | |
| 66 | ||
| 67 | /* Define this if you want to boot from 0x00000100. If you don't define | |
| 68 | * this, you will need to program the bootloader to 0xfff00000, and | |
| 69 | * get the hardware reset config words at 0xfe000000. The simplest | |
| 70 | * way to do that is to program the bootloader at both addresses. | |
| 71 | * It is suggested that you just let U-Boot live at 0x00000000. | |
| 72 | */ | |
| 73 | /* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */ | |
| 74 | /* #undef CFG_SBC_BOOT_LOW */ | |
| 75 | ||
| 76 | /* The reset command will not work as expected if the reset address does | |
| 77 | * not point to the correct address. | |
| 78 | */ | |
| 79 | ||
| 80 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
| 81 | ||
| 82 | /* What should the base address of the main FLASH be and how big is | |
| 83 | * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk | |
| 84 | * The main FLASH is whichever is connected to *CS0. U-Boot expects | |
| 85 | * this to be the SIMM. | |
| 86 | */ | |
| 87 | #define CFG_FLASH0_BASE 0xFF000000 | |
| 88 | #define CFG_FLASH0_SIZE 16 | |
| 89 | ||
| 90 | /* What should the base address of the secondary FLASH be and how big | |
| 91 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
| 92 | * to *CS6. U-Boot expects this to be the on board FLASH. If you don't | |
| 93 | * want it enabled, don't define these constants. | |
| 94 | */ | |
| 95 | #define CFG_FLASH1_BASE 0 | |
| 96 | #define CFG_FLASH1_SIZE 0 | |
| 97 | #undef CFG_FLASH1_BASE | |
| 98 | #undef CFG_FLASH1_SIZE | |
| 99 | ||
| 100 | /* What should be the base address of SDRAM DIMM (60x bus) and how big is | |
| 101 | * it (in Mbytes)? | |
| 102 | */ | |
| 103 | #define CFG_SDRAM0_BASE 0x00000000 | |
| 104 | #define CFG_SDRAM0_SIZE 64 | |
| 105 | ||
| 106 | /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the | |
| 107 | * local bus (8260 local bus is NOT cacheable!) | |
| 108 | */ | |
| 109 | /* #define CFG_LSDRAM */ | |
| 110 | #undef CFG_LSDRAM | |
| 111 | ||
| 112 | #ifdef CFG_LSDRAM | |
| 113 | /* What should be the base address of SDRAM DIMM (local bus) and how big is | |
| 114 | * it (in Mbytes)? | |
| 115 | */ | |
| 116 | #define CFG_SDRAM1_BASE 0x04000000 | |
| 117 | #define CFG_SDRAM1_SIZE 32 | |
| 118 | #else | |
| 119 | #define CFG_SDRAM1_BASE 0 | |
| 120 | #define CFG_SDRAM1_SIZE 0 | |
| 121 | #undef CFG_SDRAM1_BASE | |
| 122 | #undef CFG_SDRAM1_SIZE | |
| 123 | #endif /* CFG_LSDRAM */ | |
| 124 | ||
| 125 | /* What should be the base address of NVRAM and how big is | |
| 126 | * it (in Bytes) | |
| 127 | */ | |
| 128 | #define CFG_NVRAM_BASE_ADDR 0xFa080000 | |
| 129 | #define CFG_NVRAM_SIZE (128*1024)-16 | |
| 130 | ||
| 131 | /* The RTC is a Dallas DS1556 | |
| 132 | */ | |
| 133 | #define CONFIG_RTC_DS1556 | |
| 134 | ||
| 135 | /* What should be the base address of the LEDs and switch S0? | |
| 136 | * If you don't want them enabled, don't define this. | |
| 137 | */ | |
| 138 | #define CFG_LED_BASE 0x00000000 | |
| 139 | #undef CFG_LED_BASE | |
| 140 | ||
| 141 | /* | |
| 142 | * select serial console configuration | |
| 143 | * | |
| 144 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 145 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 146 | * for SCC). | |
| 147 | * | |
| 148 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 149 | * defined elsewhere. | |
| 150 | */ | |
| 151 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 152 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 153 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
| 154 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
| 155 | ||
| 156 | /* | |
| 157 | * select ethernet configuration | |
| 158 | * | |
| 159 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 160 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 161 | * for FCC) | |
| 162 | * | |
| 163 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 164 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed | |
| 165 | * from CONFIG_COMMANDS to remove support for networking. | |
| 166 | */ | |
| 167 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
| 168 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
| 169 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
| 170 | #define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ | |
| 171 | ||
| 172 | #if ( CONFIG_ETHER_INDEX == 3 ) | |
| 173 | ||
| 174 | /* | |
| 175 | * - Rx-CLK is CLK15 | |
| 176 | * - Tx-CLK is CLK16 | |
| 177 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
| 178 | * - Enable Half Duplex in FSMR | |
| 179 | */ | |
| 180 | # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) | |
| 181 | # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
| 182 | ||
| 183 | /* | |
| 184 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
| 185 | */ | |
| 186 | #ifdef CFG_LSDRAM | |
| 187 | #define CFG_CPMFCR_RAMTYPE 3 | |
| 188 | #else /* CFG_LSDRAM */ | |
| 189 | #define CFG_CPMFCR_RAMTYPE 0 | |
| 190 | #endif /* CFG_LSDRAM */ | |
| 191 | ||
| 192 | /* - Enable Half Duplex in FSMR */ | |
| 193 | /* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ | |
| 194 | # define CFG_FCC_PSMR 0 | |
| 195 | ||
| 196 | #else /* CONFIG_ETHER_INDEX */ | |
| 197 | # error "on EP8260 ethernet must be FCC3" | |
| 198 | #endif /* CONFIG_ETHER_INDEX */ | |
| 199 | ||
| 200 | /* | |
| 201 | * select i2c support configuration | |
| 202 | * | |
| 203 | * Supported configurations are {none, software, hardware} drivers. | |
| 204 | * If the software driver is chosen, there are some additional | |
| 205 | * configuration items that the driver uses to drive the port pins. | |
| 206 | */ | |
| 207 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 208 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
| 209 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 210 | #define CFG_I2C_SLAVE 0x7F | |
| 211 | ||
| 212 | /* | |
| 213 | * Software (bit-bang) I2C driver configuration | |
| 214 | */ | |
| 215 | #ifdef CONFIG_SOFT_I2C | |
| 216 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
| 217 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
| 218 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
| 219 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
| 220 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
| 221 | else iop->pdat &= ~0x00010000 | |
| 222 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
| 223 | else iop->pdat &= ~0x00020000 | |
| 224 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
| 225 | #endif /* CONFIG_SOFT_I2C */ | |
| 226 | ||
| 227 | /* #define CONFIG_RTC_DS174x */ | |
| 228 | ||
| 229 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
| 230 | * environment variables. Otherwise, the environment will be | |
| 231 | * put in the same sector as U-Boot, and changing variables | |
| 232 | * will erase U-Boot temporarily | |
| 233 | */ | |
| 234 | #define CFG_ENV_IN_OWN_SECT | |
| 235 | ||
| 236 | /* Define to allow the user to overwrite serial and ethaddr */ | |
| 237 | #define CONFIG_ENV_OVERWRITE | |
| 238 | ||
| 239 | /* What should the console's baud rate be? */ | |
| 240 | /* #define CONFIG_BAUDRATE 57600 */ | |
| 241 | #define CONFIG_BAUDRATE 115200 | |
| 242 | ||
| 243 | /* Ethernet MAC address */ | |
| 244 | #define CONFIG_ETHADDR 00:10:EC:00:30:8C | |
| 245 | ||
| 246 | #define CONFIG_IPADDR 192.168.254.130 | |
| 247 | #define CONFIG_SERVERIP 192.168.254.49 | |
| 248 | ||
| 249 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
| 250 | #define CONFIG_BOOTDELAY -1 | |
| 251 | ||
| 252 | /* undef this to save memory */ | |
| 253 | #define CFG_LONGHELP | |
| 254 | ||
| 255 | /* Monitor Command Prompt */ | |
| 256 | #define CFG_PROMPT "=> " | |
| 257 | ||
| 258 | /* Define this variable to enable the "hush" shell (from | |
| 259 | Busybox) as command line interpreter, thus enabling | |
| 260 | powerful command line syntax like | |
| 261 | if...then...else...fi conditionals or `&&' and '||' | |
| 262 | constructs ("shell scripts"). | |
| 263 | If undefined, you get the old, much simpler behaviour | |
| 264 | with a somewhat smapper memory footprint. | |
| 265 | */ | |
| 266 | #define CFG_HUSH_PARSER | |
| 267 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 268 | ||
| 269 | /* What U-Boot subsytems do you want enabled? */ | |
| 270 | /* | |
| 271 | */ | |
| 272 | #define CONFIG_COMMANDS ( CFG_CMD_ALL & \ | |
| 824a1ebf | 273 | ~CFG_CMD_BMP & \ |
| 5b1d7137 WD |
274 | ~CFG_CMD_BSP & \ |
| 275 | ~CFG_CMD_DCR & \ | |
| 276 | ~CFG_CMD_DHCP & \ | |
| 277 | ~CFG_CMD_DOC & \ | |
| 278 | ~CFG_CMD_EEPROM & \ | |
| 279 | ~CFG_CMD_FDC & \ | |
| 2262cfee | 280 | ~CFG_CMD_FDOS & \ |
| 5b1d7137 WD |
281 | ~CFG_CMD_HWFLOW & \ |
| 282 | ~CFG_CMD_IDE & \ | |
| 283 | ~CFG_CMD_JFFS2 & \ | |
| 284 | ~CFG_CMD_KGDB & \ | |
| 285 | ~CFG_CMD_MII & \ | |
| 71f95118 | 286 | ~CFG_CMD_MMC & \ |
| ac6dbb85 | 287 | ~CFG_CMD_NAND & \ |
| 5b1d7137 WD |
288 | ~CFG_CMD_PCI & \ |
| 289 | ~CFG_CMD_PCMCIA & \ | |
| 290 | ~CFG_CMD_SCSI & \ | |
| 1d0350ed | 291 | ~CFG_CMD_SPI & \ |
| 5b1d7137 WD |
292 | ~CFG_CMD_USB & \ |
| 293 | ~CFG_CMD_VFD & \ | |
| 294 | ~CFG_CMD_DTT ) | |
| 295 | ||
| 296 | /* Where do the internal registers live? */ | |
| 297 | #define CFG_IMMR 0xF0000000 | |
| 298 | #define CFG_DEFAULT_IMMR 0x00010000 | |
| 299 | ||
| 300 | /* Where do the on board registers (CS4) live? */ | |
| 301 | #define CFG_REGS_BASE 0xFA000000 | |
| 302 | ||
| 303 | /***************************************************************************** | |
| 304 | * | |
| 305 | * You should not have to modify any of the following settings | |
| 306 | * | |
| 307 | *****************************************************************************/ | |
| 308 | ||
| 309 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
| 310 | #define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ | |
| 311 | ||
| 312 | #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ | |
| 313 | ||
| 314 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 315 | #include <cmd_confdefs.h> | |
| 316 | ||
| 317 | /* | |
| 318 | * Miscellaneous configurable options | |
| 319 | */ | |
| 320 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 321 | # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 322 | #else | |
| 323 | # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 324 | #endif | |
| 325 | ||
| 326 | /* Print Buffer Size */ | |
| 327 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) | |
| 328 | ||
| 329 | #define CFG_MAXARGS 8 /* max number of command args */ | |
| 330 | ||
| 331 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 332 | ||
| 333 | #ifdef CFG_LSDRAM | |
| 334 | #define CFG_MEMTEST_START 0x04000000 /* memtest works on */ | |
| 335 | #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ | |
| 336 | #else | |
| 337 | #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ | |
| 338 | #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ | |
| 339 | #endif /* CFG_LSDRAM */ | |
| 340 | ||
| 341 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
| 342 | ||
| 343 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ | |
| 344 | #define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */ | |
| 345 | ||
| 346 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 347 | ||
| 348 | /* valid baudrates */ | |
| 349 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 350 | ||
| 351 | /* | |
| 352 | * Low Level Configuration Settings | |
| 353 | * (address mappings, register initial values, etc.) | |
| 354 | * You should know what you are doing if you make changes here. | |
| 355 | */ | |
| 356 | ||
| 357 | #define CFG_FLASH_BASE CFG_FLASH0_BASE | |
| 358 | #define CFG_SDRAM_BASE CFG_SDRAM0_BASE | |
| 359 | ||
| 360 | /*----------------------------------------------------------------------- | |
| 361 | * Hard Reset Configuration Words | |
| 362 | */ | |
| 363 | ||
| 364 | #if defined(CFG_SBC_BOOT_LOW) | |
| 365 | # define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
| 366 | #else | |
| 367 | # define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000) | |
| 368 | #endif /* defined(CFG_SBC_BOOT_LOW) */ | |
| 369 | ||
| 370 | /* get the HRCW ISB field from CFG_IMMR */ | |
| 371 | /* | |
| 372 | #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ | |
| 8bde7f77 WD |
373 | ((CFG_IMMR & 0x01000000) >> 7) |\ |
| 374 | ((CFG_IMMR & 0x00100000) >> 4) ) | |
| 5b1d7137 WD |
375 | |
| 376 | #define CFG_HRCW_MASTER (HRCW_EBM |\ | |
| 8bde7f77 | 377 | HRCW_L2CPC01 |\ |
| 5b1d7137 WD |
378 | CFG_SBC_HRCW_IMMR |\ |
| 379 | HRCW_APPC10 |\ | |
| 380 | HRCW_CS10PC01 |\ | |
| 381 | HRCW_MODCK_H0101 |\ | |
| 382 | CFG_SBC_HRCW_BOOT_FLAGS) | |
| 383 | */ | |
| 384 | #define CFG_HRCW_MASTER 0x10400245 | |
| 385 | ||
| 386 | /* no slaves */ | |
| 387 | #define CFG_HRCW_SLAVE1 0 | |
| 388 | #define CFG_HRCW_SLAVE2 0 | |
| 389 | #define CFG_HRCW_SLAVE3 0 | |
| 390 | #define CFG_HRCW_SLAVE4 0 | |
| 391 | #define CFG_HRCW_SLAVE5 0 | |
| 392 | #define CFG_HRCW_SLAVE6 0 | |
| 393 | #define CFG_HRCW_SLAVE7 0 | |
| 394 | ||
| 395 | /*----------------------------------------------------------------------- | |
| 396 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 397 | */ | |
| 398 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 399 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
| 400 | #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ | |
| 401 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 402 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 403 | ||
| 404 | /*----------------------------------------------------------------------- | |
| 405 | * Start addresses for the final memory configuration | |
| 406 | * (Set up by the startup code) | |
| 407 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 408 | * Note also that the logic that sets CFG_RAMBOOT is platform dependent. | |
| 409 | */ | |
| 410 | #define CFG_MONITOR_BASE TEXT_BASE | |
| 411 | ||
| 412 | ||
| 413 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 414 | # define CFG_RAMBOOT | |
| 415 | #endif | |
| 416 | ||
| 417 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 418 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 419 | ||
| 420 | /* | |
| 421 | * For booting Linux, the board info and command line data | |
| 422 | * have to be in the first 8 MB of memory, since this is | |
| 423 | * the maximum mapped by the Linux kernel during initialization. | |
| 424 | */ | |
| 425 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 426 | ||
| 427 | /*----------------------------------------------------------------------- | |
| 428 | * FLASH and environment organization | |
| 429 | */ | |
| 430 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 431 | #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
| 432 | ||
| 433 | #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ | |
| 434 | #define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
| 435 | ||
| 436 | #ifndef CFG_RAMBOOT | |
| 437 | # define CFG_ENV_IS_IN_FLASH 1 | |
| 438 | ||
| 439 | # ifdef CFG_ENV_IN_OWN_SECT | |
| 440 | # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
| 441 | # define CFG_ENV_SECT_SIZE 0x40000 | |
| 442 | # else | |
| 443 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) | |
| 444 | # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
| 445 | # define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
| 446 | # endif /* CFG_ENV_IN_OWN_SECT */ | |
| 447 | #else | |
| 448 | # define CFG_ENV_IS_IN_NVRAM 1 | |
| 449 | # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 450 | # define CFG_ENV_SIZE 0x200 | |
| 451 | #endif /* CFG_RAMBOOT */ | |
| 452 | ||
| 453 | /*----------------------------------------------------------------------- | |
| 454 | * Cache Configuration | |
| 455 | */ | |
| 456 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
| 457 | ||
| 458 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 459 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 460 | #endif | |
| 461 | ||
| 462 | /*----------------------------------------------------------------------- | |
| 463 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 464 | *----------------------------------------------------------------------- | |
| 465 | * HID0 also contains cache control - initially enable both caches and | |
| 466 | * invalidate contents, then the final state leaves only the instruction | |
| 467 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 468 | * but Soft reset does not. | |
| 469 | * | |
| 470 | * HID1 has only read-only information - nothing to set. | |
| 471 | */ | |
| 472 | #define CFG_HID0_INIT (HID0_ICE |\ | |
| 473 | HID0_DCE |\ | |
| 474 | HID0_ICFI |\ | |
| 475 | HID0_DCI |\ | |
| 476 | HID0_IFEM |\ | |
| 477 | HID0_ABE) | |
| 478 | #ifdef CFG_LSDRAM | |
| 479 | /* 8260 local bus is NOT cacheable */ | |
| 480 | #define CFG_HID0_FINAL (/*HID0_ICE |*/\ | |
| 481 | HID0_IFEM |\ | |
| 482 | HID0_ABE |\ | |
| 483 | HID0_EMCP) | |
| 484 | #else /* !CFG_LSDRAM */ | |
| 485 | #define CFG_HID0_FINAL (HID0_ICE |\ | |
| 486 | HID0_IFEM |\ | |
| 487 | HID0_ABE |\ | |
| 488 | HID0_EMCP) | |
| 489 | #endif /* CFG_LSDRAM */ | |
| 490 | ||
| 491 | #define CFG_HID2 0 | |
| 492 | ||
| 493 | /*----------------------------------------------------------------------- | |
| 494 | * RMR - Reset Mode Register | |
| 495 | *----------------------------------------------------------------------- | |
| 496 | */ | |
| 497 | #define CFG_RMR 0 | |
| 498 | ||
| 499 | /*----------------------------------------------------------------------- | |
| 500 | * BCR - Bus Configuration 4-25 | |
| 501 | *----------------------------------------------------------------------- | |
| 502 | */ | |
| 503 | /*#define CFG_BCR (BCR_EBM |\ | |
| 504 | BCR_PLDP |\ | |
| 505 | BCR_EAV |\ | |
| 506 | BCR_NPQM1) | |
| 507 | */ | |
| 508 | #define CFG_BCR 0x80C08000 | |
| 509 | /*----------------------------------------------------------------------- | |
| 510 | * SIUMCR - SIU Module Configuration 4-31 | |
| 511 | *----------------------------------------------------------------------- | |
| 512 | */ | |
| 513 | ||
| 514 | #define CFG_SIUMCR (SIUMCR_L2CPC01 |\ | |
| 8bde7f77 WD |
515 | SIUMCR_APPC10 |\ |
| 516 | SIUMCR_CS10PC01) | |
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517 | |
| 518 | ||
| 519 | /*----------------------------------------------------------------------- | |
| 520 | * SYPCR - System Protection Control 11-9 | |
| 521 | * SYPCR can only be written once after reset! | |
| 522 | *----------------------------------------------------------------------- | |
| 523 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 524 | */ | |
| 525 | #ifdef CFG_LSDRAM | |
| 526 | #define CFG_SYPCR (SYPCR_SWTC |\ | |
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527 | SYPCR_BMT |\ |
| 528 | SYPCR_PBME |\ | |
| 529 | SYPCR_LBME |\ | |
| 530 | SYPCR_SWP) | |
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531 | #else |
| 532 | #define CFG_SYPCR (SYPCR_SWTC |\ | |
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533 | SYPCR_BMT |\ |
| 534 | SYPCR_PBME |\ | |
| 535 | SYPCR_SWP) | |
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536 | #endif |
| 537 | /*----------------------------------------------------------------------- | |
| 538 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 539 | *----------------------------------------------------------------------- | |
| 540 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 541 | * and enable Time Counter | |
| 542 | */ | |
| 543 | #define CFG_TMCNTSC (TMCNTSC_SEC |\ | |
| 8bde7f77 WD |
544 | TMCNTSC_ALR |\ |
| 545 | TMCNTSC_TCF |\ | |
| 546 | TMCNTSC_TCE) | |
| 5b1d7137 WD |
547 | |
| 548 | /*----------------------------------------------------------------------- | |
| 549 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 550 | *----------------------------------------------------------------------- | |
| 551 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 552 | * Periodic timer | |
| 553 | */ | |
| 554 | /*#define CFG_PISCR (PISCR_PS |\ | |
| 8bde7f77 WD |
555 | PISCR_PTF |\ |
| 556 | PISCR_PTE)*/ | |
| 5b1d7137 WD |
557 | #define CFG_PISCR 0 |
| 558 | /*----------------------------------------------------------------------- | |
| 559 | * SCCR - System Clock Control 9-8 | |
| 560 | *----------------------------------------------------------------------- | |
| 561 | */ | |
| 562 | #define CFG_SCCR (SCCR_DFBRG01) | |
| 563 | ||
| 564 | /*----------------------------------------------------------------------- | |
| 565 | * RCCR - RISC Controller Configuration 13-7 | |
| 566 | *----------------------------------------------------------------------- | |
| 567 | */ | |
| 568 | #define CFG_RCCR 0 | |
| 569 | ||
| 570 | /*----------------------------------------------------------------------- | |
| 571 | * MPTPR - Memory Refresh Timer Prescale Register 10-32 | |
| 572 | *----------------------------------------------------------------------- | |
| 573 | */ | |
| 574 | #define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK) | |
| 575 | ||
| 576 | /* | |
| 577 | * Init Memory Controller: | |
| 578 | * | |
| 579 | * Bank Bus Machine PortSz Device | |
| 580 | * ---- --- ------- ------ ------ | |
| 581 | * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) | |
| 582 | * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) | |
| 583 | * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) | |
| 584 | * 3 unused | |
| 585 | * 4 60x GPCM 8 bit Board Regs, NVRTC | |
| 586 | * 5 unused | |
| 587 | * 6 unused | |
| 588 | * 7 unused | |
| 589 | * 8 PCMCIA | |
| 590 | * 9 unused | |
| 591 | * 10 unused | |
| 592 | * 11 unused | |
| 593 | */ | |
| 594 | ||
| 595 | /*----------------------------------------------------------------------- | |
| 596 | * BRx - Base Register | |
| 597 | * Ref: Section 10.3.1 on page 10-14 | |
| 598 | * ORx - Option Register | |
| 599 | * Ref: Section 10.3.2 on page 10-18 | |
| 600 | *----------------------------------------------------------------------- | |
| 601 | */ | |
| 602 | ||
| 603 | /* Bank 0 - FLASH | |
| 604 | * | |
| 605 | */ | |
| 606 | #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 | 607 | BRx_PS_64 |\ |
| 5b1d7137 | 608 | BRx_DECC_NONE |\ |
| 8bde7f77 WD |
609 | BRx_MS_GPCM_P |\ |
| 610 | BRx_V) | |
| 5b1d7137 WD |
611 | |
| 612 | #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ | |
| 8bde7f77 WD |
613 | ORxG_CSNT |\ |
| 614 | ORxG_ACS_DIV1 |\ | |
| 615 | ORxG_SCY_6_CLK |\ | |
| 616 | ORxG_EHTR) | |
| 5b1d7137 WD |
617 | |
| 618 | /* Bank 1 - SDRAM | |
| 619 | * PSDRAM | |
| 620 | */ | |
| 621 | #define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
622 | BRx_PS_64 |\ |
| 623 | BRx_MS_SDRAM_P |\ | |
| 624 | BRx_V) | |
| 5b1d7137 WD |
625 | |
| 626 | #define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ | |
| 8bde7f77 WD |
627 | ORxS_BPD_4 |\ |
| 628 | ORxS_ROWST_PBI1_A6 |\ | |
| 629 | ORxS_NUMR_12) | |
| 5b1d7137 WD |
630 | |
| 631 | #define CFG_PSDMR 0xC34E2462 | |
| 632 | #define CFG_PSRT 0x64 | |
| 633 | ||
| 634 | ||
| 635 | #ifdef CFG_LSDRAM | |
| 636 | /* Bank 2 - SDRAM | |
| 637 | * LSDRAM | |
| 638 | */ | |
| 639 | ||
| 640 | #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
641 | BRx_PS_32 |\ |
| 642 | BRx_MS_SDRAM_L |\ | |
| 643 | BRx_V) | |
| 5b1d7137 WD |
644 | |
| 645 | #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ | |
| 8bde7f77 WD |
646 | ORxS_BPD_4 |\ |
| 647 | ORxS_ROWST_PBI0_A9 |\ | |
| 648 | ORxS_NUMR_12) | |
| 5b1d7137 WD |
649 | |
| 650 | #define CFG_LSDMR 0x416A2562 | |
| 651 | #define CFG_LSRT 0x64 | |
| 652 | #else | |
| 653 | #define CFG_LSRT 0x0 | |
| 654 | #endif /* CFG_LSDRAM */ | |
| 655 | ||
| 656 | /* Bank 4 - On board registers | |
| 657 | * NVRTC and BCSR | |
| 658 | */ | |
| 659 | #define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
660 | BRx_PS_8 |\ |
| 661 | BRx_MS_GPCM_P |\ | |
| 662 | BRx_V) | |
| 5b1d7137 WD |
663 | /* |
| 664 | #define CFG_OR4_PRELIM (ORxG_AM_MSK |\ | |
| 8bde7f77 WD |
665 | ORxG_CSNT |\ |
| 666 | ORxG_ACS_DIV1 |\ | |
| 667 | ORxG_SCY_10_CLK |\ | |
| 668 | ORxG_TRLX) | |
| 5b1d7137 WD |
669 | */ |
| 670 | #define CFG_OR4_PRELIM 0xfff00854 | |
| 671 | ||
| 672 | /* Bank 8 - On board registers | |
| 673 | * PCMCIA (currently not working!) | |
| 674 | */ | |
| 675 | #define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ | |
| 8bde7f77 WD |
676 | BRx_PS_16 |\ |
| 677 | BRx_MS_GPCM_P |\ | |
| 678 | BRx_V) | |
| 5b1d7137 WD |
679 | |
| 680 | #define CFG_OR8_PRELIM (ORxG_AM_MSK |\ | |
| 8bde7f77 WD |
681 | ORxG_CSNT |\ |
| 682 | ORxG_ACS_DIV1 |\ | |
| 5b1d7137 | 683 | ORxG_SETA |\ |
| 8bde7f77 | 684 | ORxG_SCY_10_CLK) |
| 5b1d7137 WD |
685 | |
| 686 | /* | |
| 687 | * Internal Definitions | |
| 688 | * | |
| 689 | * Boot Flags | |
| 690 | */ | |
| 691 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 692 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 693 | ||
| 694 | #endif /* __CONFIG_H */ |