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1 | /* |
2 | * Copyright (C) 2006 Embedded Planet, LLC. | |
3 | * | |
4 | * U-Boot configuration for Embedded Planet EP82xxM boards. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
28 | #define CONFIG_MPC8260 | |
29 | #define CPU_ID_STR "MPC8270" | |
30 | ||
f836e414 | 31 | #define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ |
7ce343e4 WD |
32 | /* 256MB SDRAM / 64MB FLASH */ |
33 | ||
34 | #undef DEBUG | |
35 | ||
36 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
37 | ||
38 | /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ | |
39 | #define CONFIG_ENV_OVERWRITE | |
40 | ||
41 | /* | |
42 | * Select serial console configuration | |
43 | * | |
44 | * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
45 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
46 | * for SCC). | |
47 | */ | |
48 | #define CONFIG_CONS_ON_SMC /* Console is on SMC */ | |
49 | #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ | |
50 | #undef CONFIG_CONS_NONE /* It's not on external UART */ | |
51 | #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ | |
52 | ||
53 | #define CFG_BCSR 0xFA000000 | |
54 | ||
55 | /* | |
56 | * Select ethernet configuration | |
57 | * | |
58 | * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
59 | * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
60 | * SCC, 1-3 for FCC) | |
61 | * | |
62 | * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
63 | * must be defined elsewhere (as for the console), or CFG_CMD_NET must | |
64 | * be removed from CONFIG_COMMANDS to remove support for networking. | |
65 | */ | |
66 | #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ | |
67 | #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ | |
68 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ | |
69 | ||
70 | #define CONFIG_NET_MULTI | |
71 | ||
72 | #define CONFIG_ETHER_ON_FCC2 | |
73 | #define CONFIG_ETHER_ON_FCC3 | |
74 | ||
75 | #define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) | |
76 | #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) | |
77 | #define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
78 | #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
79 | ||
80 | #define CFG_CPMFCR_RAMTYPE 0 | |
81 | #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
82 | ||
83 | #define CONFIG_MII /* MII PHY management */ | |
84 | #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ | |
85 | ||
86 | /* | |
87 | * GPIO pins used for bit-banged MII communications | |
88 | */ | |
89 | #define MDIO_PORT 0 /* Not used - implemented in BCSR */ | |
90 | #define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) | |
91 | #define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) | |
92 | #define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) | |
93 | ||
94 | #define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ | |
95 | else *(vu_char *)(CFG_BCSR + 8) &= 0xFE | |
96 | ||
97 | #define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ | |
98 | else *(vu_char *)(CFG_BCSR + 8) &= 0xFD | |
99 | ||
100 | #define MIIDELAY udelay(1) | |
101 | ||
102 | ||
103 | #ifndef CONFIG_8260_CLKIN | |
104 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ | |
105 | #endif | |
106 | ||
107 | #define CONFIG_BAUDRATE 115200 | |
108 | ||
109 | #define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ | |
110 | ||
111 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
112 | | CFG_CMD_DHCP \ | |
113 | | CFG_CMD_ECHO \ | |
114 | | CFG_CMD_I2C \ | |
115 | | CFG_CMD_IMMAP \ | |
116 | | CFG_CMD_MII \ | |
117 | | CFG_CMD_PING \ | |
118 | | CFG_CMD_DATE \ | |
119 | | CFG_CMD_DTT \ | |
120 | | CFG_CMD_EEPROM \ | |
121 | | CFG_CMD_PCI \ | |
122 | | CFG_CMD_DIAG \ | |
123 | ) | |
124 | ||
125 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
126 | #include <cmd_confdefs.h> | |
127 | ||
128 | #define CONFIG_ETHADDR 00:10:EC:00:88:65 | |
129 | #define CONFIG_HAS_ETH1 | |
130 | #define CONFIG_ETH1ADDR 00:10:EC:80:88:65 | |
131 | #define CONFIG_IPADDR 10.0.0.245 | |
132 | #define CONFIG_HOSTNAME EP82xxM | |
133 | #define CONFIG_SERVERIP 10.0.0.26 | |
134 | #define CONFIG_GATEWAYIP 10.0.0.1 | |
135 | #define CONFIG_NETMASK 255.255.255.0 | |
136 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
137 | #define CFG_ENV_IN_OWN_SECT 1 | |
8078f1a5 | 138 | #define CONFIG_AUTO_COMPLETE 1 |
7ce343e4 WD |
139 | #define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" |
140 | ||
141 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
142 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ | |
143 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
144 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
145 | #define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ | |
146 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ | |
147 | #endif | |
148 | ||
149 | #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ | |
150 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
151 | ||
152 | /* | |
153 | * Miscellaneous configurable options | |
154 | */ | |
155 | #define CFG_HUSH_PARSER | |
156 | #define CFG_PROMPT_HUSH_PS2 "> " | |
157 | #define CFG_LONGHELP /* undef to save memory */ | |
158 | #define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ | |
159 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
160 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
161 | #else | |
162 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
163 | #endif | |
164 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
165 | #define CFG_MAXARGS 16 /* max number of command args */ | |
166 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
167 | ||
168 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
169 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
170 | ||
171 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
172 | ||
173 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
174 | ||
175 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
176 | ||
177 | /*----------------------------------------------------------------------- | |
178 | * Environment | |
179 | *----------------------------------------------------------------------*/ | |
180 | /* | |
181 | * Define here the location of the environment variables (FLASH or EEPROM). | |
182 | * Note: DENX encourages to use redundant environment in FLASH. | |
183 | */ | |
184 | #if 1 | |
185 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
186 | #else | |
187 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
188 | #endif | |
189 | ||
190 | /*----------------------------------------------------------------------- | |
191 | * FLASH related | |
192 | *----------------------------------------------------------------------*/ | |
193 | #define CFG_FLASH_BASE 0xFC000000 | |
194 | #define CFG_FLASH_CFI | |
195 | #define CFG_FLASH_CFI_DRIVER | |
196 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
197 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
198 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ | |
199 | ||
200 | #ifdef CFG_ENV_IS_IN_FLASH | |
201 | #define CFG_ENV_SECT_SIZE 0x20000 | |
202 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
203 | #endif /* CFG_ENV_IS_IN_FLASH */ | |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * I2C | |
207 | *----------------------------------------------------------------------*/ | |
208 | /* EEPROM Configuration */ | |
209 | #define CFG_EEPROM_SIZE 0x1000 | |
210 | #define CFG_I2C_EEPROM_ADDR 0x54 | |
211 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
212 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
213 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
214 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
215 | ||
216 | #ifdef CFG_ENV_IS_IN_EEPROM | |
217 | #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ | |
218 | #define CFG_ENV_OFFSET 0x0 | |
219 | #endif /* CFG_ENV_IS_IN_EEPROM */ | |
220 | ||
221 | /* RTC Configuration */ | |
222 | #define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ | |
223 | #define CFG_I2C_RTC_ADDR 0x68 | |
224 | #define CONFIG_M41T11_BASE_YEAR 1900 | |
225 | ||
226 | /* I2C SYSMON (LM75) */ | |
227 | #define CONFIG_DTT_LM75 1 | |
228 | #define CONFIG_DTT_SENSORS {0} | |
229 | #define CFG_DTT_MAX_TEMP 70 | |
230 | #define CFG_DTT_LOW_TEMP -30 | |
231 | #define CFG_DTT_HYSTERESIS 3 | |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * NVRAM Configuration | |
235 | *----------------------------------------------------------------------- | |
236 | */ | |
237 | #define CFG_NVRAM_BASE_ADDR 0xFA080000 | |
238 | #define CFG_NVRAM_SIZE (128*1024)-16 | |
239 | ||
240 | ||
241 | /*----------------------------------------------------------------------- | |
242 | * PCI stuff | |
243 | *----------------------------------------------------------------------- | |
244 | */ | |
245 | /* General PCI */ | |
246 | #define CONFIG_PCI /* include pci support */ | |
247 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
248 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
249 | #define CONFIG_PCI_BOOTDELAY 0 | |
250 | ||
251 | /* PCI Memory map (if different from default map */ | |
252 | #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ | |
253 | #define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ | |
254 | #define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ | |
255 | PICMR_PREFETCH_EN) | |
256 | ||
257 | /* | |
258 | * These are the windows that allow the CPU to access PCI address space. | |
259 | * All three PCI master windows, which allow the CPU to access PCI | |
260 | * prefetch, non prefetch, and IO space (see below), must all fit within | |
261 | * these windows. | |
262 | */ | |
263 | ||
264 | /* | |
265 | * Master window that allows the CPU to access PCI Memory (prefetch). | |
266 | * This window will be setup with the second set of Outbound ATU registers | |
267 | * in the bridge. | |
268 | */ | |
269 | ||
270 | #define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ | |
271 | #define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ | |
272 | #define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL | |
273 | #define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ | |
274 | #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) | |
275 | ||
276 | /* | |
277 | * Master window that allows the CPU to access PCI Memory (non-prefetch). | |
278 | * This window will be setup with the second set of Outbound ATU registers | |
279 | * in the bridge. | |
280 | */ | |
281 | ||
282 | #define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ | |
283 | #define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ | |
284 | #define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL | |
285 | #define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ | |
286 | #define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) | |
287 | ||
288 | /* | |
289 | * Master window that allows the CPU to access PCI IO space. | |
290 | * This window will be setup with the first set of Outbound ATU registers | |
291 | * in the bridge. | |
292 | */ | |
293 | ||
294 | #define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ | |
295 | #define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ | |
296 | #define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL | |
297 | #define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ | |
298 | #define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) | |
299 | ||
300 | ||
301 | /* PCIBR0 - for PCI IO*/ | |
302 | #define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ | |
303 | #define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ | |
304 | /* PCIBR1 - prefetch and non-prefetch regions joined together */ | |
305 | #define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL | |
306 | #define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) | |
307 | ||
308 | ||
309 | #define CFG_DIRECT_FLASH_TFTP | |
310 | ||
311 | #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) | |
312 | #define CFG_JFFS2_FIRST_BANK 0 | |
313 | #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS | |
314 | #define CFG_JFFS2_FIRST_SECTOR 0 | |
315 | #define CFG_JFFS2_LAST_SECTOR 62 | |
316 | #define CFG_JFFS2_SORT_FRAGMENTS | |
317 | #define CFG_JFFS_CUSTOM_PART | |
318 | #endif /* CFG_CMD_JFFS2 */ | |
319 | ||
320 | #if (CONFIG_COMMANDS & CFG_CMD_I2C) | |
321 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
322 | #define CFG_I2C_SPEED 100000 /* I2C speed */ | |
323 | #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ | |
324 | #endif /* CFG_CMD_I2C */ | |
325 | ||
326 | #define CFG_MONITOR_BASE TEXT_BASE | |
327 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
328 | #define CFG_RAMBOOT | |
329 | #endif | |
330 | ||
331 | #define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ | |
332 | ||
333 | #define CFG_DEFAULT_IMMR 0x00010000 | |
334 | #define CFG_IMMR 0xF0000000 | |
335 | ||
336 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
337 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ | |
338 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
339 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
340 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
341 | ||
342 | ||
343 | /* Hard reset configuration word */ | |
344 | #define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ | |
345 | /* No slaves */ | |
346 | #define CFG_HRCW_SLAVE1 0 | |
347 | #define CFG_HRCW_SLAVE2 0 | |
348 | #define CFG_HRCW_SLAVE3 0 | |
349 | #define CFG_HRCW_SLAVE4 0 | |
350 | #define CFG_HRCW_SLAVE5 0 | |
351 | #define CFG_HRCW_SLAVE6 0 | |
352 | #define CFG_HRCW_SLAVE7 0 | |
353 | ||
354 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
355 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
356 | ||
357 | #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ | |
358 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
359 | ||
360 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ | |
361 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
362 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
363 | #endif | |
364 | ||
365 | #define CFG_HID0_INIT 0 | |
366 | #define CFG_HID0_FINAL 0 | |
367 | ||
368 | #define CFG_HID2 0 | |
369 | ||
370 | #define CFG_SIUMCR 0x02610000 | |
371 | #define CFG_SYPCR 0xFFFF0689 | |
372 | #define CFG_BCR 0x8080E000 | |
373 | #define CFG_SCCR 0x00000001 | |
374 | ||
375 | #define CFG_RMR 0 | |
376 | #define CFG_TMCNTSC 0x000000C3 | |
377 | #define CFG_PISCR 0x00000083 | |
378 | #define CFG_RCCR 0 | |
379 | ||
380 | #define CFG_MPTPR 0x0A00 | |
381 | #define CFG_PSDMR 0xC432246E | |
382 | #define CFG_PSRT 0x32 | |
383 | ||
384 | #define CFG_SDRAM_BASE 0x00000000 | |
385 | #define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) | |
386 | #define CFG_SDRAM_OR 0xF0002900 | |
387 | ||
388 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) | |
389 | #define CFG_OR0_PRELIM 0xFC000882 | |
390 | #define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001) | |
391 | #define CFG_OR4_PRELIM 0xFFF00050 | |
392 | ||
393 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
394 | ||
395 | #endif /* __CONFIG_H */ |