projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6a994e5b NI |
1 | /* |
| 2 | * include/configs/gose.h | |
| 3 | * | |
| 4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
| 5 | * | |
| 6 | * SPDX-License-Identifier: GPL-2.0 | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __GOSE_H | |
| 10 | #define __GOSE_H | |
| 11 | ||
| 12 | #undef DEBUG | |
| 13 | #define CONFIG_R8A7793 | |
| 14 | #define CONFIG_RMOBILE_BOARD_STRING "Gose" | |
| 6a994e5b | 15 | |
| 5ca6dfe6 | 16 | #include "rcar-gen2-common.h" |
| 6a994e5b NI |
17 | |
| 18 | #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) | |
| 19 | #define CONFIG_SYS_TEXT_BASE 0x70000000 | |
| 20 | #else | |
| 21 | #define CONFIG_SYS_TEXT_BASE 0xE6304000 | |
| 22 | #endif | |
| 23 | ||
| 6a994e5b NI |
24 | /* STACK */ |
| 25 | #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) | |
| 26 | #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC | |
| 27 | #else | |
| 28 | #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC | |
| 29 | #endif | |
| 30 | ||
| 31 | #define STACK_AREA_SIZE 0xC000 | |
| 32 | #define LOW_LEVEL_MERAM_STACK \ | |
| 33 | (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) | |
| 34 | ||
| 35 | /* MEMORY */ | |
| 5ca6dfe6 NI |
36 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 |
| 37 | #define RCAR_GEN2_SDRAM_SIZE 0x40000000 | |
| 38 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 | |
| 6a994e5b NI |
39 | |
| 40 | /* SCIF */ | |
| 41 | #define CONFIG_SCIF_CONSOLE | |
| 6a994e5b NI |
42 | |
| 43 | /* FLASH */ | |
| 44 | #define CONFIG_SYS_NO_FLASH | |
| 45 | #define CONFIG_SPI | |
| 46 | #define CONFIG_SH_QSPI | |
| 6a994e5b | 47 | |
| f0261243 | 48 | /* SH Ether */ |
| f0261243 NI |
49 | #define CONFIG_SH_ETHER |
| 50 | #define CONFIG_SH_ETHER_USE_PORT 0 | |
| 51 | #define CONFIG_SH_ETHER_PHY_ADDR 0x1 | |
| 52 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII | |
| 53 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK | |
| 54 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE | |
| 55 | #define CONFIG_PHYLIB | |
| 56 | #define CONFIG_PHY_MICREL | |
| 57 | #define CONFIG_BITBANGMII | |
| 58 | #define CONFIG_BITBANGMII_MULTI | |
| 59 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 | |
| 60 | ||
| 6a994e5b NI |
61 | /* Board Clock */ |
| 62 | #define RMOBILE_XTAL_CLK 20000000u | |
| 63 | #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK | |
| 64 | #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) | |
| 6a994e5b NI |
65 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
| 66 | ||
| 67 | /* I2C */ | |
| 68 | #define CONFIG_SYS_I2C | |
| 69 | #define CONFIG_SYS_I2C_SH | |
| 70 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 71 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 | |
| 6a994e5b | 72 | #define CONFIG_SYS_I2C_SH_SPEED0 400000 |
| 6a994e5b | 73 | #define CONFIG_SYS_I2C_SH_SPEED1 400000 |
| 6a994e5b NI |
74 | #define CONFIG_SYS_I2C_SH_SPEED2 400000 |
| 75 | #define CONFIG_SH_I2C_DATA_HIGH 4 | |
| 76 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
| 77 | #define CONFIG_SH_I2C_CLOCK 10000000 | |
| 78 | ||
| 79 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ | |
| 80 | ||
| d3ee73fc NI |
81 | /* USB */ |
| 82 | #define CONFIG_USB_STORAGE | |
| 83 | #define CONFIG_USB_EHCI | |
| 84 | #define CONFIG_USB_EHCI_RMOBILE | |
| 85 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
| 86 | ||
| 8e2e5886 NI |
87 | /* Module stop status bits */ |
| 88 | /* INTC-RT */ | |
| 89 | #define CONFIG_SMSTP0_ENA 0x00400000 | |
| 90 | /* MSIF */ | |
| 91 | #define CONFIG_SMSTP2_ENA 0x00002000 | |
| 92 | /* INTC-SYS, IRQC */ | |
| 93 | #define CONFIG_SMSTP4_ENA 0x00000180 | |
| 94 | /* SCIF0 */ | |
| 95 | #define CONFIG_SMSTP7_ENA 0x00200000 | |
| 96 | ||
| e2abab69 NI |
97 | /* SDHI */ |
| 98 | #define CONFIG_MMC | |
| e2abab69 NI |
99 | #define CONFIG_GENERIC_MMC |
| 100 | #define CONFIG_SH_SDHI_FREQ 97500000 | |
| 101 | ||
| 6a994e5b | 102 | #endif /* __GOSE_H */ |