[people/ms/u-boot.git] / include / configs / gr_ep2s60.h

/* Configuration header file for Gaisler Research AB's Template
 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
 * Development board Stratix II edition, with the FPGA device
 * EP2S60.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2008
 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H__
#define __CONFIG_H__

#define CONFIG_DISPLAY_BOARDINFO

/*
 * High Level Configuration Options
 * (easy to change)
 */

/* Altera NIOS Development board, Stratix II board */
#define CONFIG_GR_EP2S60	1

/* CPU / AMBA BUS configuration */
#define CONFIG_SYS_CLK_FREQ	96000000	/* 96MHz */

/* Define this is the GR-2S60-MEZZ mezzanine is available and you
 * want to use the USB and GRETH functionality of the board
 */
#undef GR_2S60_MEZZ

#ifdef GR_2S60_MEZZ
#define USE_GRETH 1
#define USE_GRUSB 1
#endif

/*
 * Serial console configuration
 */
#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * Supported commands
 */
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_IRQ

/* USB support */
#if USE_GRUSB
#define CONFIG_USB_UHCI
/* Enable needed helper functions */
#define CONFIG_SYS_STDIO_DEREGISTER	/* needs stdio_deregister */
#endif

/*
 * Autobooting
 */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
	"scratch=40800000\0"					\
	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
	""

#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.20
#define CONFIG_IPADDR 192.168.0.207
#define CONFIG_ROOTPATH "/export/rootfs"
#define CONFIG_HOSTNAME  ml401
#define CONFIG_BOOTFILE "/uImage"

#define CONFIG_BOOTCOMMAND	"run flash_self"

/* Memory MAP
 *
 *  Flash:
 *  |--------------------------------|
 *  | 0x00000000 Text & Data & BSS   | *
 *  |            for Monitor         | *
 *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
 *  | UNUSED / Growth                | * 256kb
 *  |--------------------------------|
 *  | 0x00050000 Base custom area    | *
 *  |            kernel / FS         | *
 *  |                                | * Rest of Flash
 *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
 *  | END-0x00008000 Environment     | * 32kb
 *  |--------------------------------|
 *
 *
 *
 *  Main Memory:
 *  |--------------------------------|
 *  | UNUSED / scratch area          |
 *  |                                |
 *  |                                |
 *  |                                |
 *  |                                |
 *  |--------------------------------|
 *  | Monitor .Text / .DATA / .BSS   | * 512kb
 *  | Relocated!                     | *
 *  |--------------------------------|
 *  | Monitor Malloc                 | * 128kb (contains relocated environment)
 *  |--------------------------------|
 *  | Monitor/kernel STACK           | * 64kb
 *  |--------------------------------|
 *  | Page Table for MMU systems     | * 2k
 *  |--------------------------------|
 *  | PROM Code accessed from Linux  | * 6kb-128b
 *  |--------------------------------|
 *  | Global data (avail from kernel)| * 128b
 *  |--------------------------------|
 *
 */

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
/*#define CONFIG_SYS_NO_FLASH		1*/
#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */

#define PHYS_FLASH_SECT_SIZE	0x00010000	/* 64 KB sectors */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */

/*** CFI CONFIG ***/
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
/* Buffered writes (32byte/go) instead of single accesses */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * Environment settings
 */
/*#define CONFIG_ENV_IS_NOWHERE 1*/
#define CONFIG_ENV_IS_IN_FLASH	1
/* CONFIG_ENV_ADDR need to be at sector boundary */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		0x02000000
#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)

/* no SRAM available */
#undef CONFIG_SYS_SRAM_BASE
#undef CONFIG_SYS_SRAM_SIZE

#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE		(0x10000-32)

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)

/* relocated monitor area */
#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)

/* make un relocated address from relocated address */
#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))

/*
 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
 * with a PHY is attached the GRETH can be used on this board.
 * Define USE_GRETH in order to use the mezzanine provided PHY with the
 * onchip GRETH network MAC, note that this is not supported by the
 * template design.
 */
#ifndef USE_GRETH

/* USE SMC91C111 MAC */
#define CONFIG_SMC91111          1
#define CONFIG_SMC91111_BASE		0x20000300	/* chip select 3         */
#define CONFIG_SMC_USE_32_BIT		1	/* 32 bit bus  */
#undef  CONFIG_SMC_91111_EXT_PHY	/* we use internal phy   */
/*#define CONFIG_SHOW_ACTIVITY*/
#define CONFIG_NET_RETRY_COUNT		10	/* # of retries          */

#else

/* USE GRETH Ethernet Driver */
#define CONFIG_GRETH	1
#endif

#define CONFIG_PHY_ADDR	 0x00

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

/***** Gaisler GRLIB IP-Cores Config ********/

#define CONFIG_SYS_GRLIB_SDRAM    0

/* No SDRAM Configuration */
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1

/* See, GRLIB Docs (grip.pdf) on how to set up
 * These the memory controller registers.
 */
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1  (0x10f800ff | (1<<11))
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2  0x00000000
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3  0x00000000

/* GRLIB FT-MCTRL configuration */
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1  (0x10f800ff | (1<<11))
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2  0x00000000
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3  0x00000000

/* DDR controller */
#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL  0xa900830a

/* no DDR2 Controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1

/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
6940383d DH	1	/* Configuration header file for Gaisler Research AB's Template
	2	* design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
	3	* Development board Stratix II edition, with the FPGA device
	4	* EP2S60.
	5	*
	6	* (C) Copyright 2003-2005
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* (C) Copyright 2008
	10	* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
	11	*
3765b3e7	12	* SPDX-License-Identifier: GPL-2.0+
6940383d DH	13	*/
	14
	15	#ifndef __CONFIG_H__
	16	#define __CONFIG_H__
	17
4c547754	18	#define CONFIG_DISPLAY_BOARDINFO
a62bba15	19
6940383d DH	20	/*
	21	* High Level Configuration Options
	22	* (easy to change)
	23	*/
	24
6940383d	25	/* Altera NIOS Development board, Stratix II board */
53677ef1	26	#define CONFIG_GR_EP2S60 1
6940383d DH	27
6940383d DH	28	/* CPU / AMBA BUS configuration */
53677ef1	29	#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
6940383d	30
6940383d DH	31	/* Define this is the GR-2S60-MEZZ mezzanine is available and you
	32	* want to use the USB and GRETH functionality of the board
	33	*/
	34	#undef GR_2S60_MEZZ
	35
	36	#ifdef GR_2S60_MEZZ
	37	#define USE_GRETH 1
	38	#define USE_GRUSB 1
	39	#endif
	40
	41	/*
	42	* Serial console configuration
	43	*/
	44	#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
6d0f6bcf	45	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6940383d DH	46
	47	/* Partitions */
	48	#define CONFIG_DOS_PARTITION
	49	#define CONFIG_MAC_PARTITION
	50	#define CONFIG_ISO_PARTITION
	51
	52	/*
	53	* Supported commands
	54	*/
6940383d	55	#define CONFIG_CMD_REGINFO
6940383d DH	56	#define CONFIG_CMD_DIAG
	57	#define CONFIG_CMD_IRQ
	58
	59	/* USB support */
	60	#if USE_GRUSB
	61	#define CONFIG_USB_UHCI
6940383d	62	/* Enable needed helper functions */
52cb4d4f	63	#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
6940383d DH	64	#endif
	65
	66	/*
	67	* Autobooting
	68	*/
6940383d DH	69
	70	#define CONFIG_PREBOOT "echo;" \
	71	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	72	"echo"
	73
	74	#undef CONFIG_BOOTARGS
	75
	76	#define CONFIG_EXTRA_ENV_SETTINGS \
	77	"netdev=eth0\0" \
	78	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
	79	"nfsroot=${serverip}:${rootpath}\0" \
	80	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
	81	"addip=setenv bootargs ${bootargs} " \
	82	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	83	":${hostname}:${netdev}:off panic=1\0" \
	84	"flash_nfs=run nfsargs addip;" \
	85	"bootm ${kernel_addr}\0" \
	86	"flash_self=run ramargs addip;" \
	87	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	88	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
	89	"scratch=40800000\0" \
3a2b9f28	90	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
6940383d DH	91	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
	92	""
	93
	94	#define CONFIG_NETMASK 255.255.255.0
	95	#define CONFIG_GATEWAYIP 192.168.0.1
	96	#define CONFIG_SERVERIP 192.168.0.20
	97	#define CONFIG_IPADDR 192.168.0.207
8b3637c6	98	#define CONFIG_ROOTPATH "/export/rootfs"
6940383d	99	#define CONFIG_HOSTNAME ml401
b3f44c21	100	#define CONFIG_BOOTFILE "/uImage"
6940383d DH	101
	102	#define CONFIG_BOOTCOMMAND "run flash_self"
	103
	104	/* Memory MAP
	105	*
	106	* Flash:
	107	* \|--------------------------------\|
	108	* \| 0x00000000 Text & Data & BSS \| *
	109	* \| for Monitor \| *
	110	* \| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\| *
	111	* \| UNUSED / Growth \| * 256kb
	112	* \|--------------------------------\|
	113	* \| 0x00050000 Base custom area \| *
	114	* \| kernel / FS \| *
	115	* \| \| * Rest of Flash
	116	* \|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\|
	117	* \| END-0x00008000 Environment \| * 32kb
	118	* \|--------------------------------\|
	119	*
	120	*
	121	*
	122	* Main Memory:
	123	* \|--------------------------------\|
	124	* \| UNUSED / scratch area \|
	125	* \| \|
	126	* \| \|
	127	* \| \|
	128	* \| \|
	129	* \|--------------------------------\|
	130	* \| Monitor .Text / .DATA / .BSS \| * 512kb
	131	* \| Relocated! \| *
	132	* \|--------------------------------\|
	133	* \| Monitor Malloc \| * 128kb (contains relocated environment)
	134	* \|--------------------------------\|
	135	* \| Monitor/kernel STACK \| * 64kb
	136	* \|--------------------------------\|
	137	* \| Page Table for MMU systems \| * 2k
	138	* \|--------------------------------\|
	139	* \| PROM Code accessed from Linux \| * 6kb-128b
	140	* \|--------------------------------\|
	141	* \| Global data (avail from kernel)\| * 128b
	142	* \|--------------------------------\|
	143	*
	144	*/
	145
	146	/*
	147	* Flash configuration (8,16 or 32 MB)
	148	* TEXT base always at 0xFFF00000
	149	* ENV_ADDR always at 0xFFF40000
	150	* FLASH_BASE at 0xFC000000 for 64 MB
	151	* 0xFE000000 for 32 MB
	152	* 0xFF000000 for 16 MB
	153	* 0xFF800000 for 8 MB
	154	*/
6d0f6bcf JCPV	155	/#define CONFIG_SYS_NO_FLASH 1/
	156	#define CONFIG_SYS_FLASH_BASE 0x00000000
	157	#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
6940383d DH	158
6940383d DH	159	#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
6d0f6bcf JCPV	160	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
6d0f6bcf JCPV	161	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
6940383d	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	164	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	165	#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	166	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	167	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
6940383d DH	168
6940383d DH	169	/* CFI CONFIG */
6d0f6bcf	170	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
00b1883a	171	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf	172	#define CONFIG_SYS_FLASH_CFI
6940383d	173	/* Bypass cache when reading regs from flash memory */
6d0f6bcf	174	#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
6940383d	175	/* Buffered writes (32byte/go) instead of single accesses */
6d0f6bcf	176	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
6940383d DH	177
	178	/*
	179	* Environment settings
	180	*/
93f6d725	181	/#define CONFIG_ENV_IS_NOWHERE 1/
5a1aceb0	182	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	183	/* CONFIG_ENV_ADDR need to be at sector boundary */
	184	#define CONFIG_ENV_SIZE 0x8000
	185	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	186	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
6940383d DH	187	#define CONFIG_ENV_OVERWRITE 1
	188
	189	/*
	190	* Memory map
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	193	#define CONFIG_SYS_SDRAM_SIZE 0x02000000
	194	#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
6940383d DH	195
6940383d DH	196	/* no SRAM available */
6d0f6bcf JCPV	197	#undef CONFIG_SYS_SRAM_BASE
6d0f6bcf JCPV	198	#undef CONFIG_SYS_SRAM_SIZE
6940383d	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
	201	#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
	202	#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
6940383d	203
25ddd1fb	204	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
6940383d	205
25ddd1fb	206	#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
6d0f6bcf	207	#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
6940383d	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
6d0f6bcf JCPV	210	#define CONFIG_SYS_STACK_SIZE (0x10000-32)
6940383d	211
14d0a02a	212	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	213	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	214	# define CONFIG_SYS_RAMBOOT 1
6940383d DH	215	#endif
6940383d DH	216
6d0f6bcf JCPV	217	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
	218	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	219	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6940383d	220
6d0f6bcf JCPV	221	#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
6d0f6bcf JCPV	222	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
6940383d DH	223
6940383d DH	224	/* relocated monitor area */
6d0f6bcf JCPV	225	#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
6d0f6bcf JCPV	226	#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
6940383d DH	227
6940383d DH	228	/* make un relocated address from relocated address */
14d0a02a	229	#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
6940383d DH	230
	231	/*
	232	* Ethernet configuration uses on board SMC91C111, however if a mezzanine
	233	* with a PHY is attached the GRETH can be used on this board.
	234	* Define USE_GRETH in order to use the mezzanine provided PHY with the
	235	* onchip GRETH network MAC, note that this is not supported by the
	236	* template design.
	237	*/
	238	#ifndef USE_GRETH
	239
	240	/* USE SMC91C111 MAC */
7194ab80	241	#define CONFIG_SMC91111 1
6940383d DH	242	#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
	243	#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
	244	#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
	245	/#define CONFIG_SHOW_ACTIVITY/
	246	#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
	247
	248	#else
	249
	250	/* USE GRETH Ethernet Driver */
6940383d	251	#define CONFIG_GRETH 1
1e1f3536	252	#endif
6940383d	253
6940383d DH	254	#define CONFIG_PHY_ADDR 0x00
	255
	256	/*
	257	* Miscellaneous configurable options
	258	*/
6d0f6bcf	259	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6940383d	260	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	261	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6940383d	262	#else
6d0f6bcf	263	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6940383d	264	#endif
6d0f6bcf JCPV	265	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	266	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	267	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6940383d	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	270	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6940383d	271
6d0f6bcf	272	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6940383d	273
6940383d DH	274	/*-----------------------------------------------------------------------
	275	* USB stuff
	276	*-----------------------------------------------------------------------
	277	*/
	278	#define CONFIG_USB_CLOCK 0x0001BBBB
	279	#define CONFIG_USB_CONFIG 0x00005000
	280
	281	/*** Gaisler GRLIB IP-Cores Config ******/
	282
6d0f6bcf	283	#define CONFIG_SYS_GRLIB_SDRAM 0
6940383d	284
cff009ed DH	285	/* No SDRAM Configuration */
	286	#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
	287
6940383d DH	288	/* See, GRLIB Docs (grip.pdf) on how to set up
	289	* These the memory controller registers.
	290	*/
cff009ed DH	291	#define CONFIG_SYS_GRLIB_ESA_MCTRL1
	292	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff \| (1<<11))
	293	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
	294	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
	295
	296	/* GRLIB FT-MCTRL configuration */
	297	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
	298	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff \| (1<<11))
	299	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
	300	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
	301
	302	/* DDR controller */
	303	#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
	304	#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
	305
	306	/* no DDR2 Controller */
	307	#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
6940383d	308
6940383d DH	309	/* default kernel command line */
	310	#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
	311
	312	#endif /* __CONFIG_H */