[people/ms/u-boot.git] / include / configs / gr_xc3s_1500.h

/* Configuration header file for Gaisler GR-XC3S-1500
 * spartan board.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007
 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H__
#define __CONFIG_H__

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_GRXC3S1500	1	/* ... on GR-XC3S-1500 board */

/* CPU / AMBA BUS configuration */
#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */

/*
 * Serial console configuration
 */
#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * Supported commands
 */
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_IRQ

/*
 * Autobooting
 */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
	"scratch=40200000\0"					\
	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
	""

#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.20
#define CONFIG_IPADDR 192.168.0.206
#define CONFIG_ROOTPATH "/export/rootfs"
#define CONFIG_HOSTNAME  grxc3s1500
#define CONFIG_BOOTFILE "/uImage"

#define CONFIG_BOOTCOMMAND	"run flash_self"

/* Memory MAP
 *
 *  Flash:
 *  |--------------------------------|
 *  | 0x00000000 Text & Data & BSS   | *
 *  |            for Monitor         | *
 *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
 *  | UNUSED / Growth                | * 256kb
 *  |--------------------------------|
 *  | 0x00050000 Base custom area    | *
 *  |            kernel / FS         | *
 *  |                                | * Rest of Flash
 *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
 *  | END-0x00008000 Environment     | * 32kb
 *  |--------------------------------|
 *
 *
 *
 *  Main Memory:
 *  |--------------------------------|
 *  | UNUSED / scratch area          |
 *  |                                |
 *  |                                |
 *  |                                |
 *  |                                |
 *  |--------------------------------|
 *  | Monitor .Text / .DATA / .BSS   | * 256kb
 *  | Relocated!                     | *
 *  |--------------------------------|
 *  | Monitor Malloc                 | * 128kb (contains relocated environment)
 *  |--------------------------------|
 *  | Monitor/kernel STACK           | * 64kb
 *  |--------------------------------|
 *  | Page Table for MMU systems     | * 2k
 *  |--------------------------------|
 *  | PROM Code accessed from Linux  | * 6kb-128b
 *  |--------------------------------|
 *  | Global data (avail from kernel)| * 128b
 *  |--------------------------------|
 *
 */

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
/*#define CONFIG_SYS_NO_FLASH		1*/
#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_SYS_FLASH_SIZE		0x00800000

#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */

/*** CFI CONFIG ***/
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
/* Bypass cache when reading regs from flash memory */
#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
/* Buffered writes (32byte/go) instead of single accesses */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * Environment settings
 */
/*#define CONFIG_ENV_IS_NOWHERE 1*/
#define CONFIG_ENV_IS_IN_FLASH	1
/* CONFIG_ENV_ADDR need to be at sector boundary */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		0x4000000
#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)

/* no SRAM available */
#undef CONFIG_SYS_SRAM_BASE
#undef CONFIG_SYS_SRAM_SIZE

/* Always Run U-Boot from SDRAM */
#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
#define CONFIG_SYS_STACK_SIZE		(0x10000-32)

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)

/* relocated monitor area */
#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)

/* make un relocated address from relocated address */
#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))

/*
 * Ethernet configuration
 */
#define CONFIG_GRETH	1

#define CONFIG_PHY_ADDR	 0x00

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Various low-level settings
 */

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

/***** Gaisler GRLIB IP-Cores Config ********/

#define CONFIG_SYS_GRLIB_SDRAM    0

/* No SDRAM Configuration */
#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1

/* See, GRLIB Docs (grip.pdf) on how to set up
 * These the memory controller registers.
 */
#define CONFIG_SYS_GRLIB_ESA_MCTRL1
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1   (0x000000ff | (1<<11))
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2   0x82206000
#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3   0x00136000

/* GRLIB FT-MCTRL configuration */
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1   (0x000000ff | (1<<11))
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2   0x82206000
#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3   0x00136000

/* no DDR controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1

/* no DDR2 Controller */
#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1

/* default kernel command line */
#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
71d7e4c0 DH	1	/* Configuration header file for Gaisler GR-XC3S-1500
	2	* spartan board.
	3	*
	4	* (C) Copyright 2003-2005
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* (C) Copyright 2007
	8	* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
71d7e4c0 DH	11	*/
	12
	13	#ifndef __CONFIG_H__
	14	#define __CONFIG_H__
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
	20
71d7e4c0 DH	21	#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */
	22
	23	/* CPU / AMBA BUS configuration */
53677ef1	24	#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
71d7e4c0	25
71d7e4c0 DH	26	/*
	27	* Serial console configuration
	28	*/
	29	#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
6d0f6bcf	30	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
71d7e4c0 DH	31
	32	/* Partitions */
	33	#define CONFIG_DOS_PARTITION
	34	#define CONFIG_MAC_PARTITION
	35	#define CONFIG_ISO_PARTITION
	36
	37	/*
	38	* Supported commands
	39	*/
71d7e4c0	40	#define CONFIG_CMD_REGINFO
71d7e4c0 DH	41	#define CONFIG_CMD_DIAG
	42	#define CONFIG_CMD_IRQ
	43
	44	/*
	45	* Autobooting
	46	*/
71d7e4c0 DH	47
	48	#define CONFIG_PREBOOT "echo;" \
	49	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	50	"echo"
	51
	52	#undef CONFIG_BOOTARGS
	53
	54	#define CONFIG_EXTRA_ENV_SETTINGS \
	55	"netdev=eth0\0" \
	56	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
	57	"nfsroot=${serverip}:${rootpath}\0" \
	58	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
	59	"addip=setenv bootargs ${bootargs} " \
	60	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	61	":${hostname}:${netdev}:off panic=1\0" \
	62	"flash_nfs=run nfsargs addip;" \
	63	"bootm ${kernel_addr}\0" \
	64	"flash_self=run ramargs addip;" \
	65	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	66	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
	67	"scratch=40200000\0" \
3a2b9f28	68	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
71d7e4c0 DH	69	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
	70	""
	71
	72	#define CONFIG_NETMASK 255.255.255.0
	73	#define CONFIG_GATEWAYIP 192.168.0.1
	74	#define CONFIG_SERVERIP 192.168.0.20
	75	#define CONFIG_IPADDR 192.168.0.206
8b3637c6	76	#define CONFIG_ROOTPATH "/export/rootfs"
71d7e4c0	77	#define CONFIG_HOSTNAME grxc3s1500
b3f44c21	78	#define CONFIG_BOOTFILE "/uImage"
71d7e4c0 DH	79
	80	#define CONFIG_BOOTCOMMAND "run flash_self"
	81
	82	/* Memory MAP
	83	*
	84	* Flash:
	85	* \|--------------------------------\|
	86	* \| 0x00000000 Text & Data & BSS \| *
	87	* \| for Monitor \| *
	88	* \| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\| *
	89	* \| UNUSED / Growth \| * 256kb
	90	* \|--------------------------------\|
	91	* \| 0x00050000 Base custom area \| *
	92	* \| kernel / FS \| *
	93	* \| \| * Rest of Flash
	94	* \|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\|
	95	* \| END-0x00008000 Environment \| * 32kb
	96	* \|--------------------------------\|
	97	*
	98	*
	99	*
	100	* Main Memory:
	101	* \|--------------------------------\|
	102	* \| UNUSED / scratch area \|
	103	* \| \|
	104	* \| \|
	105	* \| \|
	106	* \| \|
	107	* \|--------------------------------\|
	108	* \| Monitor .Text / .DATA / .BSS \| * 256kb
	109	* \| Relocated! \| *
	110	* \|--------------------------------\|
	111	* \| Monitor Malloc \| * 128kb (contains relocated environment)
	112	* \|--------------------------------\|
	113	* \| Monitor/kernel STACK \| * 64kb
	114	* \|--------------------------------\|
	115	* \| Page Table for MMU systems \| * 2k
	116	* \|--------------------------------\|
	117	* \| PROM Code accessed from Linux \| * 6kb-128b
	118	* \|--------------------------------\|
	119	* \| Global data (avail from kernel)\| * 128b
	120	* \|--------------------------------\|
	121	*
	122	*/
	123
	124	/*
	125	* Flash configuration (8,16 or 32 MB)
	126	* TEXT base always at 0xFFF00000
	127	* ENV_ADDR always at 0xFFF40000
	128	* FLASH_BASE at 0xFC000000 for 64 MB
	129	* 0xFE000000 for 32 MB
	130	* 0xFF000000 for 16 MB
	131	* 0xFF800000 for 8 MB
	132	*/
6d0f6bcf JCPV	133	/#define CONFIG_SYS_NO_FLASH 1/
	134	#define CONFIG_SYS_FLASH_BASE 0x00000000
	135	#define CONFIG_SYS_FLASH_SIZE 0x00800000
71d7e4c0 DH	136
71d7e4c0 DH	137	#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
6d0f6bcf JCPV	138	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
6d0f6bcf JCPV	139	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
71d7e4c0	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	142	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	143	#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	144	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	145	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
71d7e4c0 DH	146
71d7e4c0 DH	147	/* CFI CONFIG */
6d0f6bcf	148	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
00b1883a	149	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf	150	#define CONFIG_SYS_FLASH_CFI
71d7e4c0	151	/* Bypass cache when reading regs from flash memory */
6d0f6bcf	152	#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
71d7e4c0	153	/* Buffered writes (32byte/go) instead of single accesses */
6d0f6bcf	154	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71d7e4c0 DH	155
	156	/*
	157	* Environment settings
	158	*/
93f6d725	159	/#define CONFIG_ENV_IS_NOWHERE 1/
5a1aceb0	160	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	161	/* CONFIG_ENV_ADDR need to be at sector boundary */
	162	#define CONFIG_ENV_SIZE 0x8000
	163	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	164	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
71d7e4c0 DH	165	#define CONFIG_ENV_OVERWRITE 1
	166
	167	/*
	168	* Memory map
	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	171	#define CONFIG_SYS_SDRAM_SIZE 0x4000000
	172	#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
71d7e4c0 DH	173
71d7e4c0 DH	174	/* no SRAM available */
6d0f6bcf JCPV	175	#undef CONFIG_SYS_SRAM_BASE
6d0f6bcf JCPV	176	#undef CONFIG_SYS_SRAM_SIZE
71d7e4c0 DH	177
71d7e4c0 DH	178	/* Always Run U-Boot from SDRAM */
6d0f6bcf JCPV	179	#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
	180	#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
	181	#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
71d7e4c0	182
25ddd1fb	183	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
71d7e4c0	184
25ddd1fb	185	#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
6d0f6bcf	186	#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
71d7e4c0	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
6d0f6bcf JCPV	189	#define CONFIG_SYS_STACK_SIZE (0x10000-32)
71d7e4c0	190
14d0a02a	191	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	192	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	193	# define CONFIG_SYS_RAMBOOT 1
71d7e4c0 DH	194	#endif
71d7e4c0 DH	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	197	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	198	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
71d7e4c0	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
6d0f6bcf JCPV	201	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
71d7e4c0 DH	202
71d7e4c0 DH	203	/* relocated monitor area */
6d0f6bcf JCPV	204	#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
6d0f6bcf JCPV	205	#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
71d7e4c0 DH	206
71d7e4c0 DH	207	/* make un relocated address from relocated address */
14d0a02a	208	#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
71d7e4c0 DH	209
	210	/*
	211	* Ethernet configuration
	212	*/
	213	#define CONFIG_GRETH 1
71d7e4c0	214
71d7e4c0 DH	215	#define CONFIG_PHY_ADDR 0x00
	216
	217	/*
	218	* Miscellaneous configurable options
	219	*/
6d0f6bcf	220	#define CONFIG_SYS_LONGHELP /* undef to save memory */
71d7e4c0	221	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	222	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
71d7e4c0	223	#else
6d0f6bcf	224	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
71d7e4c0	225	#endif
6d0f6bcf JCPV	226	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	227	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	228	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
71d7e4c0	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	231	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
71d7e4c0	232
6d0f6bcf	233	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
71d7e4c0	234
71d7e4c0 DH	235	/*
	236	* Various low-level settings
	237	*/
	238
	239	/*-----------------------------------------------------------------------
	240	* USB stuff
	241	*-----------------------------------------------------------------------
	242	*/
	243	#define CONFIG_USB_CLOCK 0x0001BBBB
	244	#define CONFIG_USB_CONFIG 0x00005000
	245
	246	/*** Gaisler GRLIB IP-Cores Config ******/
	247
6d0f6bcf	248	#define CONFIG_SYS_GRLIB_SDRAM 0
71d7e4c0	249
cff009ed DH	250	/* No SDRAM Configuration */
	251	#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
	252
71d7e4c0 DH	253	/* See, GRLIB Docs (grip.pdf) on how to set up
	254	* These the memory controller registers.
	255	*/
cff009ed DH	256	#define CONFIG_SYS_GRLIB_ESA_MCTRL1
	257	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff \| (1<<11))
	258	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
	259	#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000
71d7e4c0	260
cff009ed DH	261	/* GRLIB FT-MCTRL configuration */
	262	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
	263	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff \| (1<<11))
	264	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
	265	#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000
71d7e4c0 DH	266
71d7e4c0 DH	267	/* no DDR controller */
cff009ed	268	#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
71d7e4c0 DH	269
71d7e4c0 DH	270	/* no DDR2 Controller */
cff009ed	271	#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
71d7e4c0	272
71d7e4c0 DH	273	/* default kernel command line */
	274	#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
	275
	276	#endif /* __CONFIG_H */