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8966f337 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Config header file for Hymod board | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
37 | #define CONFIG_HYMOD 1 /* ...on a Hymod board */ | |
9c4c5ae3 | 38 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
8966f337 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
41 | ||
8966f337 WD |
42 | #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ |
43 | ||
44 | /* | |
45 | * select serial console configuration | |
46 | * | |
47 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
48 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
49 | * for SCC). | |
50 | * | |
51 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
52 | * defined elsewhere (for example, on the cogent platform, there are serial | |
53 | * ports on the motherboard which are used for the serial console - see | |
54 | * cogent/cma101/serial.[ch]). | |
55 | */ | |
56 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
57 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
58 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
59 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
60 | #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
61 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
62 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ | |
63 | ||
64 | /* | |
65 | * select ethernet configuration | |
66 | * | |
67 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
68 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
69 | * for FCC) | |
70 | * | |
71 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
72 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed | |
73 | * from CONFIG_COMMANDS to remove support for networking. | |
74 | */ | |
75 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
76 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
77 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
78 | #define CONFIG_ETHER_INDEX 1 /* which channel for ether */ | |
6dd652fa WD |
79 | #define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ |
80 | ||
81 | #ifdef CONFIG_ETHER_ON_FCC | |
8966f337 WD |
82 | |
83 | #if (CONFIG_ETHER_INDEX == 1) | |
84 | ||
85 | /* | |
86 | * - Rx-CLK is CLK10 | |
87 | * - Tx-CLK is CLK11 | |
88 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
89 | * - Enable Full Duplex in FSMR | |
90 | */ | |
91 | # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) | |
92 | # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) | |
93 | # define CFG_CPMFCR_RAMTYPE 0 | |
94 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
95 | ||
6dd652fa WD |
96 | # define MDIO_PORT 0 /* Port A */ |
97 | # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ | |
98 | # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ | |
99 | ||
8966f337 WD |
100 | #elif (CONFIG_ETHER_INDEX == 2) |
101 | ||
102 | /* | |
103 | * - Rx-CLK is CLK13 | |
104 | * - Tx-CLK is CLK14 | |
105 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
106 | * - Enable Full Duplex in FSMR | |
107 | */ | |
108 | # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
109 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
110 | # define CFG_CPMFCR_RAMTYPE 0 | |
111 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
112 | ||
6dd652fa WD |
113 | # define MDIO_PORT 0 /* Port A */ |
114 | # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ | |
115 | # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ | |
116 | ||
8966f337 WD |
117 | #elif (CONFIG_ETHER_INDEX == 3) |
118 | ||
119 | /* | |
120 | * - Rx-CLK is CLK15 | |
121 | * - Tx-CLK is CLK16 | |
122 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
123 | * - Enable Full Duplex in FSMR | |
124 | */ | |
125 | # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) | |
126 | # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
127 | # define CFG_CPMFCR_RAMTYPE 0 | |
128 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
129 | ||
6dd652fa WD |
130 | # define MDIO_PORT 0 /* Port A */ |
131 | # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ | |
132 | # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ | |
133 | ||
8966f337 WD |
134 | #endif /* CONFIG_ETHER_INDEX */ |
135 | ||
6dd652fa WD |
136 | #define CONFIG_MII /* MII PHY management */ |
137 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
138 | ||
139 | #define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) | |
140 | #define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) | |
141 | #define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) | |
142 | ||
143 | #define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ | |
144 | else iop->pdat &= ~MDIO_DATA_PINMASK | |
145 | ||
146 | #define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ | |
147 | else iop->pdat &= ~MDIO_CLCK_PINMASK | |
148 | ||
149 | #define MIIDELAY udelay(1) | |
150 | ||
151 | #endif /* CONFIG_ETHER_ON_FCC */ | |
152 | ||
8966f337 WD |
153 | |
154 | /* other options */ | |
155 | #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ | |
6dd652fa | 156 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ |
8966f337 WD |
157 | |
158 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
159 | #ifdef DEBUG | |
160 | #define CONFIG_8260_CLKIN 33333333 /* in Hz */ | |
161 | #else | |
162 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
163 | #endif | |
164 | ||
165 | #if defined(CONFIG_CONS_USE_EXTC) | |
166 | #define CONFIG_BAUDRATE 115200 | |
167 | #else | |
6dd652fa | 168 | #define CONFIG_BAUDRATE 9600 |
8966f337 WD |
169 | #endif |
170 | ||
171 | /* default ip addresses - these will be overridden */ | |
172 | #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ | |
173 | #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ | |
174 | ||
6dd652fa WD |
175 | #define CONFIG_LAST_STAGE_INIT |
176 | ||
48d5d102 JL |
177 | /* |
178 | * Command line configuration. | |
179 | */ | |
180 | #include <config_cmd_all.h> | |
181 | ||
182 | #undef CONFIG_CMD_BEDBUG | |
183 | #undef CONFIG_CMD_BMP | |
184 | #undef CONFIG_CMD_DISPLAY | |
185 | #undef CONFIG_CMD_DOC | |
186 | #undef CONFIG_CMD_EXT2 | |
187 | #undef CONFIG_CMD_FDC | |
188 | #undef CONFIG_CMD_FDOS | |
189 | #undef CONFIG_CMD_FPGA | |
190 | #undef CONFIG_CMD_HWFLOW | |
191 | #undef CONFIG_CMD_IDE | |
192 | #undef CONFIG_CMD_JFFS2 | |
193 | #undef CONFIG_CMD_NAND | |
194 | #undef CONFIG_CMD_MMC | |
195 | #undef CONFIG_CMD_PCMCIA | |
196 | #undef CONFIG_CMD_PCI | |
197 | #undef CONFIG_CMD_USB | |
198 | #undef CONFIG_CMD_REISER | |
199 | #undef CONFIG_CMD_SCSI | |
200 | #undef CONFIG_CMD_SPI | |
201 | #undef CONFIG_CMD_UNIVERSE | |
202 | #undef CONFIG_CMD_VFD | |
203 | #undef CONFIG_CMD_XIMG | |
204 | ||
8966f337 WD |
205 | |
206 | #ifdef DEBUG | |
207 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
6dd652fa WD |
208 | #else |
209 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
210 | #define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ | |
211 | #define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ | |
212 | /* Be selective on what keys can delay or stop the autoboot process | |
213 | * To stop use: " " | |
214 | */ | |
215 | #define CONFIG_AUTOBOOT_KEYED | |
216 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ | |
217 | "press <SPACE> to stop\n" | |
218 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
219 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
220 | #define DEBUG_BOOTKEYS 0 | |
8966f337 WD |
221 | #endif |
222 | ||
48d5d102 | 223 | #if defined(CONFIG_CMD_KGDB) |
8966f337 WD |
224 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
225 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
226 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
227 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
228 | #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
229 | #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ | |
230 | #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ | |
231 | # if defined(CONFIG_KGDB_USE_EXTC) | |
592c5cab | 232 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
8966f337 | 233 | # else |
6dd652fa | 234 | #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ |
8966f337 WD |
235 | # endif |
236 | #endif | |
237 | ||
238 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
239 | ||
240 | #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ | |
241 | ||
242 | /* | |
243 | * Hymod specific configurable options | |
244 | */ | |
245 | #undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */ | |
246 | ||
247 | /* | |
248 | * Miscellaneous configurable options | |
249 | */ | |
250 | #define CFG_LONGHELP /* undef to save memory */ | |
251 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
48d5d102 | 252 | #if defined(CONFIG_CMD_KGDB) |
8966f337 WD |
253 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
254 | #else | |
255 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
256 | #endif | |
257 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
258 | #define CFG_MAXARGS 16 /* max number of command args */ | |
259 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
260 | ||
261 | #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ | |
262 | #define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ | |
263 | ||
6dd652fa WD |
264 | #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ |
265 | ||
8966f337 WD |
266 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
267 | ||
268 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
269 | ||
270 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
271 | ||
272 | #define CFG_I2C_SPEED 50000 | |
273 | #define CFG_I2C_SLAVE 0x7e | |
274 | ||
275 | /* these are for the ST M24C02 2kbit serial i2c eeprom */ | |
276 | #define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ | |
277 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
6dd652fa WD |
278 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
279 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
280 | ||
281 | #define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ | |
282 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ | |
283 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
284 | ||
285 | #define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ | |
286 | ||
8966f337 WD |
287 | #define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ |
288 | ||
6dd652fa WD |
289 | /* |
290 | * standard dtt sensor configuration - bottom bit will determine local or | |
291 | * remote sensor of the ADM1021, the rest determines index into | |
292 | * CFG_DTT_ADM1021 array below. | |
293 | * | |
294 | * On HYMOD board, the remote sensor should be connected to the MPC8260 | |
295 | * temperature diode thingy, but an errata said this didn't work and | |
296 | * should be disabled - so it isn't connected. | |
297 | */ | |
298 | #if 0 | |
299 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
300 | #else | |
301 | #define CONFIG_DTT_SENSORS { 0 } | |
302 | #endif | |
303 | ||
304 | /* | |
305 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). | |
306 | * there will be one entry in this array for each two (dummy) sensors in | |
307 | * CONFIG_DTT_SENSORS. | |
308 | * | |
309 | * For HYMOD board: | |
310 | * - only one ADM1021 | |
311 | * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) | |
312 | * - conversion rate 0x02 = 0.25 conversions/second | |
313 | * - ALERT ouput disabled | |
314 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
315 | * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) | |
316 | */ | |
317 | #define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } | |
318 | ||
8966f337 WD |
319 | /* |
320 | * Low Level Configuration Settings | |
321 | * (address mappings, register initial values, etc.) | |
322 | * You should know what you are doing if you make changes here. | |
323 | */ | |
324 | ||
325 | /*----------------------------------------------------------------------- | |
326 | * Hard Reset Configuration Words | |
327 | * | |
328 | * if you change bits in the HRCW, you must also change the CFG_* | |
329 | * defines for the various registers affected by the HRCW e.g. changing | |
330 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
331 | */ | |
332 | #ifdef DEBUG | |
333 | #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ | |
334 | HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ | |
335 | HRCW_MODCK_H0010) | |
336 | #else | |
337 | #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ | |
338 | HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ | |
339 | HRCW_MODCK_H0101) | |
340 | #endif | |
341 | /* no slaves so just duplicate the master hrcw */ | |
342 | #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER | |
343 | #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER | |
344 | #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER | |
345 | #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER | |
346 | #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER | |
347 | #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER | |
348 | #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER | |
349 | ||
350 | /*----------------------------------------------------------------------- | |
351 | * Internal Memory Mapped Register | |
352 | */ | |
353 | #define CFG_IMMR 0xF0000000 | |
354 | ||
355 | /*----------------------------------------------------------------------- | |
356 | * Definitions for initial stack pointer and data area (in DPRAM) | |
357 | */ | |
358 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
359 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
360 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
361 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
362 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
363 | ||
364 | /*----------------------------------------------------------------------- | |
365 | * Start addresses for the final memory configuration | |
366 | * (Set up by the startup code) | |
367 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
368 | */ | |
369 | #define CFG_SDRAM_BASE 0x00000000 | |
370 | #define CFG_FLASH_BASE TEXT_BASE | |
371 | #define CFG_MONITOR_BASE TEXT_BASE | |
372 | #define CFG_FPGA_BASE 0x80000000 | |
373 | /* | |
374 | * unfortunately, CFG_MONITOR_LEN must include the | |
375 | * (very large i.e. 256kB) environment flash sector | |
376 | */ | |
377 | #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ | |
378 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
379 | ||
380 | /* | |
381 | * For booting Linux, the board info and command line data | |
382 | * have to be in the first 8 MB of memory, since this is | |
383 | * the maximum mapped by the Linux kernel during initialization. | |
384 | */ | |
385 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ | |
386 | ||
387 | /*----------------------------------------------------------------------- | |
388 | * FLASH organization | |
389 | */ | |
390 | #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ | |
391 | #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ | |
392 | ||
393 | #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ | |
394 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
395 | ||
8966f337 | 396 | #define CFG_ENV_IS_IN_FLASH 1 |
592c5cab | 397 | #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
8966f337 WD |
398 | #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ |
399 | #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) | |
400 | ||
401 | /*----------------------------------------------------------------------- | |
402 | * Cache Configuration | |
403 | */ | |
404 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
48d5d102 | 405 | #if defined(CONFIG_CMD_KGDB) |
8966f337 WD |
406 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
407 | #endif | |
408 | ||
409 | /*----------------------------------------------------------------------- | |
410 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
411 | *----------------------------------------------------------------------- | |
412 | * HID0 also contains cache control - initially enable both caches and | |
413 | * invalidate contents, then the final state leaves only the instruction | |
414 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
415 | * but Soft reset does not. | |
416 | * | |
417 | * HID1 has only read-only information - nothing to set. | |
418 | */ | |
419 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ | |
420 | HID0_IFEM|HID0_ABE) | |
421 | #ifdef DEBUG | |
422 | #define CFG_HID0_FINAL 0 | |
423 | #else | |
424 | #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) | |
425 | #endif | |
426 | #define CFG_HID2 0 | |
427 | ||
428 | /*----------------------------------------------------------------------- | |
429 | * RMR - Reset Mode Register 5-5 | |
430 | *----------------------------------------------------------------------- | |
431 | * turn on Checkstop Reset Enable | |
432 | */ | |
433 | #ifdef DEBUG | |
434 | #define CFG_RMR 0 | |
435 | #else | |
436 | #define CFG_RMR RMR_CSRE | |
437 | #endif | |
438 | ||
439 | /*----------------------------------------------------------------------- | |
440 | * BCR - Bus Configuration 4-25 | |
441 | *----------------------------------------------------------------------- | |
442 | */ | |
443 | #define CFG_BCR (BCR_ETM) | |
444 | ||
445 | /*----------------------------------------------------------------------- | |
446 | * SIUMCR - SIU Module Configuration 4-31 | |
447 | *----------------------------------------------------------------------- | |
448 | */ | |
449 | #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ | |
450 | SIUMCR_APPC10|SIUMCR_MMR11) | |
451 | ||
452 | /*----------------------------------------------------------------------- | |
453 | * SYPCR - System Protection Control 4-35 | |
454 | * SYPCR can only be written once after reset! | |
455 | *----------------------------------------------------------------------- | |
456 | * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable | |
457 | */ | |
458 | #if defined(CONFIG_WATCHDOG) | |
459 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
460 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
461 | #else | |
462 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
463 | SYPCR_SWRI|SYPCR_SWP) | |
464 | #endif /* CONFIG_WATCHDOG */ | |
465 | ||
466 | /*----------------------------------------------------------------------- | |
467 | * TMCNTSC - Time Counter Status and Control 4-40 | |
468 | *----------------------------------------------------------------------- | |
469 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
470 | * and enable Time Counter | |
471 | */ | |
472 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
473 | ||
474 | /*----------------------------------------------------------------------- | |
475 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
476 | *----------------------------------------------------------------------- | |
477 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
478 | * Periodic timer | |
479 | */ | |
480 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
481 | ||
482 | /*----------------------------------------------------------------------- | |
483 | * SCCR - System Clock Control 9-8 | |
484 | *----------------------------------------------------------------------- | |
485 | * Ensure DFBRG is Divide by 16 | |
486 | */ | |
487 | #define CFG_SCCR (SCCR_DFBRG01) | |
488 | ||
489 | /*----------------------------------------------------------------------- | |
490 | * RCCR - RISC Controller Configuration 13-7 | |
491 | *----------------------------------------------------------------------- | |
492 | */ | |
493 | #define CFG_RCCR 0 | |
494 | ||
495 | /* | |
496 | * Init Memory Controller: | |
497 | * | |
498 | * Bank Bus Machine PortSz Device | |
499 | * ---- --- ------- ------ ------ | |
500 | * 0 60x GPCM 32 bit FLASH | |
501 | * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) | |
502 | * 2 60x SDRAM 64 bit SDRAM | |
503 | * 3 Local UPMC 8 bit Main Xilinx configuration | |
504 | * 4 Local GPCM 32 bit Main Xilinx register mode | |
505 | * 5 Local UPMB 32 bit Main Xilinx port mode | |
506 | * 6 Local UPMC 8 bit Mezz Xilinx configuration | |
507 | */ | |
508 | ||
509 | /* | |
510 | * Bank 0 - FLASH | |
511 | * | |
512 | * Quotes from the HYMOD IO Board Reference manual: | |
513 | * | |
514 | * "The flash memory is two Intel StrataFlash chips, each configured for | |
515 | * 16 bit operation and connected to give a 32 bit wide port." | |
516 | * | |
517 | * "The chip select logic is configured to respond to both *CS0 and *CS1. | |
518 | * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. | |
519 | * It is suggested that bank 0 be read-only and bank 1 be read/write. The | |
520 | * FLASH will then appear as ROM during boot." | |
521 | * | |
522 | * Initially, we are only going to use bank 0 in read/write mode. | |
523 | */ | |
524 | ||
525 | /* 32 bit, read-write, GPCM on 60x bus */ | |
526 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\ | |
527 | BRx_PS_32|BRx_MS_GPCM_P|BRx_V) | |
528 | /* up to 32 Mb */ | |
529 | #define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) | |
530 | ||
531 | /* | |
532 | * Bank 2 - SDRAM | |
533 | * | |
534 | * Quotes from the HYMOD IO Board Reference manual: | |
535 | * | |
536 | * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a | |
537 | * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous | |
538 | * dynamic random access memory organised as 4 banks by 4096 rows by 512 | |
539 | * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." | |
540 | * | |
541 | * "The locations in SDRAM are accessed using multiplexed address pins to | |
542 | * specify row and column. The pins also act to specify commands. The state | |
543 | * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP | |
544 | * pin may function as a row address or as the AUTO PRECHARGE control line, | |
545 | * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 | |
546 | * address lines to be configured to the required multiplexing scheme." | |
547 | */ | |
548 | ||
549 | #define CFG_SDRAM_SIZE 64 | |
550 | ||
551 | /* 64 bit, read-write, SDRAM on 60x bus */ | |
552 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\ | |
553 | BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) | |
554 | /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ | |
555 | #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\ | |
556 | ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) | |
557 | ||
558 | /* | |
559 | * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: | |
560 | * | |
561 | * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 | |
562 | * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 | |
563 | * as bank select, A7 is output on SDA10 during an ACTIVATE command, | |
564 | * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, | |
565 | * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
566 | * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE | |
567 | * command is 2 clocks, earliest timing for PRECHARGE after last data | |
568 | * was read is 1 clock, earliest timing for PRECHARGE after last data | |
569 | * was written is 1 clock, CAS Latency is 2. | |
570 | */ | |
571 | ||
572 | #define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ | |
573 | PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ | |
574 | PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ | |
575 | PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ | |
576 | PSDMR_WRC_1C|PSDMR_CL_2) | |
577 | ||
578 | /* | |
579 | * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh | |
580 | * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register | |
581 | * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer | |
582 | * Prescaler, hence the P instead of the R). The refresh timer period is given | |
583 | * by (note that there was a change in the 8260 UM Errata): | |
584 | * | |
585 | * TimerPeriod = (PSRT + 1) / Fmptc | |
586 | * | |
587 | * where Fmptc is the BusClock divided by PTP. i.e. | |
588 | * | |
589 | * TimerPeriod = (PSRT + 1) / (BusClock / PTP) | |
590 | * | |
591 | * or | |
592 | * | |
593 | * TImerPeriod = (PTP * (PSRT + 1)) / BusClock | |
594 | * | |
595 | * The requirement for the Toshiba TC59SM716FTL-10 is that there must be | |
596 | * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 | |
597 | * = 15.625 usecs. | |
598 | * | |
599 | * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 | |
600 | * appear to be reasonable. | |
601 | */ | |
602 | ||
603 | #ifdef DEBUG | |
604 | #define CFG_PSRT 39 | |
605 | #define CFG_MPTPR MPTPR_PTP_DIV8 | |
606 | #else | |
607 | #define CFG_PSRT 31 | |
608 | #define CFG_MPTPR MPTPR_PTP_DIV32 | |
609 | #endif | |
610 | ||
611 | /* | |
612 | * Banks 3,4,5 and 6 - FPGA access | |
613 | * | |
614 | * Quotes from the HYMOD IO Board Reference manual: | |
615 | * | |
616 | * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made | |
617 | * for configuring an optional FPGA on the mezzanine interface. | |
618 | * | |
619 | * Access to the FPGAs may be divided into several catagories: | |
620 | * | |
621 | * 1. Configuration | |
622 | * 2. Register mode access | |
623 | * 3. Port mode access | |
624 | * | |
625 | * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be | |
626 | * configured only (mode 1). Consequently there are four access types. | |
627 | * | |
628 | * To improve interface performance and simplify software design, the four | |
629 | * possible access types are separately mapped to different memory banks. | |
630 | * | |
631 | * All are accessed using the local bus." | |
632 | * | |
633 | * Device Mode Memory Bank Machine Port Size Access | |
634 | * | |
635 | * Main Configuration 3 UPMC 8bit R/W | |
636 | * Main Register 4 GPCM 32bit R/W | |
637 | * Main Port 5 UPMB 32bit R/W | |
638 | * Mezzanine Configuration 6 UPMC 8bit W/O | |
639 | * | |
640 | * "Note that mezzanine mode 1 access is write-only." | |
641 | */ | |
642 | ||
643 | /* all the bank sizes must be a power of two, greater or equal to 32768 */ | |
644 | #define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE) | |
645 | #define FPGA_MAIN_CFG_SIZE 32768 | |
646 | #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) | |
647 | #define FPGA_MAIN_REG_SIZE 32768 | |
648 | #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) | |
649 | #define FPGA_MAIN_PORT_SIZE 32768 | |
650 | #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) | |
651 | #define FPGA_MEZZ_CFG_SIZE 32768 | |
652 | ||
653 | /* 8 bit, read-write, UPMC */ | |
654 | #define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) | |
655 | /* up to 32Kbyte, burst inhibit */ | |
656 | #define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) | |
657 | ||
658 | /* 32 bit, read-write, GPCM */ | |
659 | #define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) | |
660 | /* up to 32Kbyte */ | |
661 | #define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) | |
662 | ||
663 | /* 32 bit, read-write, UPMB */ | |
664 | #define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) | |
665 | /* up to 32Kbyte */ | |
666 | #define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) | |
667 | ||
668 | /* 8 bit, write-only, UPMC */ | |
669 | #define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) | |
670 | /* up to 32Kbyte, burst inhibit */ | |
671 | #define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) | |
672 | ||
673 | /*----------------------------------------------------------------------- | |
674 | * MBMR - Machine B Mode 10-27 | |
675 | *----------------------------------------------------------------------- | |
676 | */ | |
677 | #define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ | |
678 | ||
679 | /*----------------------------------------------------------------------- | |
680 | * MCMR - Machine C Mode 10-27 | |
681 | *----------------------------------------------------------------------- | |
682 | */ | |
683 | #define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ | |
684 | ||
685 | /* | |
686 | * FPGA I/O Port/Bit information | |
687 | */ | |
688 | ||
689 | #define FPGA_MAIN_PROG_PORT IOPIN_PORTA | |
690 | #define FPGA_MAIN_PROG_PIN 4 /* PA4 */ | |
691 | #define FPGA_MAIN_INIT_PORT IOPIN_PORTA | |
692 | #define FPGA_MAIN_INIT_PIN 5 /* PA5 */ | |
693 | #define FPGA_MAIN_DONE_PORT IOPIN_PORTA | |
694 | #define FPGA_MAIN_DONE_PIN 6 /* PA6 */ | |
695 | ||
696 | #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA | |
697 | #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ | |
698 | #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA | |
699 | #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ | |
700 | #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA | |
701 | #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ | |
702 | #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA | |
703 | #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ | |
704 | ||
6dd652fa WD |
705 | /* |
706 | * FPGA Interrupt configuration | |
707 | */ | |
708 | #define FPGA_MAIN_IRQ SIU_INT_IRQ2 | |
709 | ||
8966f337 WD |
710 | /* |
711 | * Internal Definitions | |
712 | * | |
713 | * Boot Flags | |
714 | */ | |
715 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
716 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
717 | ||
700a0c64 WD |
718 | /* |
719 | * JFFS2 partitions | |
720 | * | |
721 | */ | |
722 | /* No command line, one static partition, whole device */ | |
723 | #undef CONFIG_JFFS2_CMDLINE | |
724 | #define CONFIG_JFFS2_DEV "nor0" | |
725 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
726 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
727 | ||
728 | /* mtdparts command line support */ | |
729 | /* | |
730 | #define CONFIG_JFFS2_CMDLINE | |
731 | #define MTDIDS_DEFAULT "" | |
732 | #define MTDPARTS_DEFAULT "" | |
733 | */ | |
734 | ||
8966f337 | 735 | #endif /* __CONFIG_H */ |