[people/ms/u-boot.git] / include / configs / ibf-dsp561.h

/*
 * U-Boot - Configuration file for IBF-DSP561 board
 */

#ifndef __CONFIG_IBF_DSP561__H__
#define __CONFIG_IBF_DSP561__H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf561-0.5
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			24
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	9
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x377
#define CONFIG_EBIU_SDGCTL_VAL	0x91998d
#define CONFIG_EBIU_SDBCTL_VAL	0x15

#define CONFIG_EBIU_AMGCTL_VAL	0x3F
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)

/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_DRIVER_AX88180	1
#define AX88180_BASE		0x2c000000
#define CONFIG_HOSTNAME		ibf-dsp561

/*
 * Flash Settings
 */
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
/* The BF561-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x12000	/* Total Size of Environment Sector */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1

/*
 * Misc Settings
 */
#define CONFIG_UART_CONSOLE	0

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
0f52b560	1	/*
a187559e	2	* U-Boot - Configuration file for IBF-DSP561 board
0f52b560 HH	3	*/
	4
	5	#ifndef __CONFIG_IBF_DSP561__H__
	6	#define __CONFIG_IBF_DSP561__H__
	7
f348ab85	8	#include <asm/config-pre.h>
0f52b560	9
0f52b560 HH	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf561-0.5
0f52b560 HH	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
0f52b560 HH	15
0f52b560 HH	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 25000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 24
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 5
	38
0f52b560 HH	39	/*
	40	* Memory Settings
	41	*/
	42	#define CONFIG_MEM_ADD_WDTH 9
	43	#define CONFIG_MEM_SIZE 64
	44
	45	#define CONFIG_EBIU_SDRRC_VAL 0x377
	46	#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
	47	#define CONFIG_EBIU_SDBCTL_VAL 0x15
	48
	49	#define CONFIG_EBIU_AMGCTL_VAL 0x3F
	50	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	51	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	52
	53	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	54	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	55
5cbbabc2 HH	56	/*
	57	* Network Settings
	58	*/
	59	#define ADI_CMDS_NETWORK 1
5cbbabc2 HH	60	#define CONFIG_DRIVER_AX88180 1
	61	#define AX88180_BASE 0x2c000000
	62	#define CONFIG_HOSTNAME ibf-dsp561
5cbbabc2	63
0f52b560 HH	64	/*
	65	* Flash Settings
	66	*/
	67	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	68	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	69	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
	70	#define CONFIG_SYS_FLASH_BASE 0x20000000
	71	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	72	#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
	73	/* The BF561-EZKIT uses a top boot flash */
	74	#define CONFIG_ENV_IS_IN_FLASH 1
d2ab733c MF	75	#define CONFIG_ENV_OFFSET 0x4000
d2ab733c MF	76	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
0f52b560	77	#define CONFIG_ENV_SIZE 0x2000
0d3fd562	78	#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */
0f52b560 HH	79	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	80	#define ENV_IS_EMBEDDED
	81	#else
76d82187	82	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
0f52b560	83	#endif
9ff67e5e MF	84	#ifdef ENV_IS_EMBEDDED
	85	/* WARNING - the following is hand-optimized to fit within
	86	* the sector before the environment sector. If it throws
	87	* an error during compilation remove an object here to get
	88	* it linked after the configuration sector.
	89	*/
	90	# define LDS_BOARD_TEXT \
e2906a59 MY	91	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	92	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	93	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	94	common/env_embedded.o (.text*);
9ff67e5e	95	#endif
0f52b560	96
0f52b560 HH	97	/*
	98	* I2C Settings
	99	*/
ea818dbb HS	100	#define CONFIG_SYS_I2C
ea818dbb HS	101	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
beb60e77 MF	102	#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
beb60e77 MF	103	#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
0f52b560	104
0f52b560 HH	105	/*
	106	* Misc Settings
	107	*/
	108	#define CONFIG_UART_CONSOLE 0
	109
0f52b560 HH	110	/*
	111	* Pull in common ADI header for remaining command/environment setup
	112	*/
	113	#include <configs/bfin_adi_common.h>
	114
f348ab85	115	#endif