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| Commit | Line | Data |
|---|---|---|
| 029faf3e SR |
1 | /* |
| 2 | * (C) Copyright 2009-2010 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * icon.h - configuration for Mosaixtech ICON (440SPe) | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | */ | |
| 34 | #define CONFIG_ICON 1 /* Board is icon */ | |
| 35 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 36 | #define CONFIG_440 1 /* ... PPC440 family */ | |
| 37 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
| 38 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
| 39 | #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ | |
| 40 | ||
| 41 | /* | |
| 42 | * Include common defines/options for all AMCC eval boards | |
| 43 | */ | |
| 44 | #define CONFIG_HOSTNAME icon | |
| 45 | #include "amcc-common.h" | |
| 46 | ||
| 47 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
| 48 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ | |
| 49 | ||
| 50 | /* | |
| 51 | * Base addresses -- Note these are effective addresses where the | |
| 52 | * actual resources get mapped (not physical addresses) | |
| 53 | */ | |
| 54 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ | |
| 029faf3e SR |
55 | #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ |
| 56 | ||
| 57 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ | |
| 58 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
| 59 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE | |
| 60 | ||
| 61 | #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ | |
| 62 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ | |
| 63 | #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ | |
| 64 | ||
| 65 | #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 | |
| 66 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 | |
| 67 | #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 | |
| 68 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 | |
| 69 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 | |
| 70 | #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 | |
| 71 | ||
| 72 | /* base address of inbound PCIe window */ | |
| 73 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL | |
| 74 | ||
| 75 | /* System RAM mapped to PCI space */ | |
| 76 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE | |
| 77 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE | |
| 78 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
| 79 | ||
| 80 | #define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ | |
| 81 | #define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 | |
| 82 | #define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 | |
| 83 | ||
| 84 | #define CONFIG_SYS_FLASH_SIZE (64 << 20) | |
| 85 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ | |
| 86 | #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 | |
| 87 | #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 | |
| 88 | #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ | |
| 89 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) | |
| 90 | ||
| 91 | /* | |
| 92 | * Initial RAM & stack pointer (placed in internal SRAM) | |
| 93 | */ | |
| 94 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
| 95 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
| 96 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ | |
| 97 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */ | |
| 98 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */ | |
| 99 | ||
| 100 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ | |
| 101 | CONFIG_SYS_GBL_DATA_SIZE) | |
| 800eb096 | 102 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
| 029faf3e SR |
103 | |
| 104 | /* | |
| 105 | * Serial Port | |
| 106 | */ | |
| 550650dd | 107 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 029faf3e SR |
108 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
| 109 | ||
| 110 | /* | |
| 111 | * DDR2 SDRAM | |
| 112 | */ | |
| 113 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
| 114 | #define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ | |
| 115 | #define CONFIG_DDR_ECC /* with ECC support */ | |
| 116 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ | |
| 117 | ||
| 118 | /* | |
| 119 | * I2C | |
| 120 | */ | |
| 121 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ | |
| 122 | ||
| 123 | #define CONFIG_I2C_MULTI_BUS | |
| 124 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ | |
| 125 | ||
| 126 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 127 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
| 128 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 129 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 130 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 131 | ||
| 132 | /* I2C bootstrap EEPROM */ | |
| 133 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
| 134 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
| 135 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 8 | |
| 136 | ||
| 137 | /* I2C RTC */ | |
| 138 | #define CONFIG_RTC_M41T11 | |
| 139 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ | |
| 140 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 141 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
| 142 | ||
| 86caca1c AG |
143 | /* |
| 144 | * Video options | |
| 145 | */ | |
| 146 | #define CONFIG_VIDEO | |
| 147 | ||
| 148 | #ifdef CONFIG_VIDEO | |
| 149 | #define CONFIG_VIDEO_SM501 | |
| 150 | #define CONFIG_VIDEO_SM501_32BPP | |
| 151 | #define CONFIG_VIDEO_SM501_PCI | |
| 152 | #define VIDEO_FB_LITTLE_ENDIAN | |
| 153 | #define CONFIG_CFB_CONSOLE | |
| 154 | #define CONFIG_VIDEO_LOGO | |
| 155 | #define CONFIG_CONSOLE_EXTRA_INFO | |
| 156 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 157 | #define CONFIG_VIDEO_SW_CURSOR | |
| 158 | #define CONFIG_VIDEO_BMP_RLE8 | |
| 159 | #define CONFIG_SPLASH_SCREEN | |
| 160 | #define CFG_CONSOLE_IS_IN_ENV | |
| 161 | #endif | |
| 162 | ||
| 029faf3e SR |
163 | /* |
| 164 | * Environment | |
| 165 | */ | |
| 166 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ | |
| 167 | ||
| 168 | /* | |
| 169 | * Default environment variables | |
| 170 | */ | |
| 171 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 172 | CONFIG_AMCC_DEF_ENV \ | |
| 173 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 174 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 175 | "kernel_addr=fc000000\0" \ | |
| 176 | "fdt_addr=fc1e0000\0" \ | |
| 177 | "ramdisk_addr=fc200000\0" \ | |
| 178 | "pciconfighost=1\0" \ | |
| 179 | "pcie_mode=RP:RP:RP\0" \ | |
| 180 | "" | |
| 181 | ||
| 182 | /* | |
| 183 | * Commands additional to the ones defined in amcc-common.h | |
| 184 | */ | |
| 185 | #define CONFIG_CMD_CHIP_CONFIG | |
| 186 | #define CONFIG_CMD_DATE | |
| 187 | #define CONFIG_CMD_EXT2 | |
| 188 | #define CONFIG_CMD_FAT | |
| 189 | #define CONFIG_CMD_PCI | |
| 190 | #define CONFIG_CMD_SDRAM | |
| 191 | #define CONFIG_CMD_SNTP | |
| 86caca1c AG |
192 | #ifdef CONFIG_VIDEO |
| 193 | #define CONFIG_CMD_BMP | |
| 194 | #endif | |
| 029faf3e SR |
195 | |
| 196 | #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ | |
| 197 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
| 198 | #define CONFIG_HAS_ETH0 | |
| 199 | #define CONFIG_PHY_RESET /* reset phy upon startup */ | |
| 200 | #define CONFIG_PHY_RESET_DELAY 1000 | |
| 201 | #define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ | |
| 202 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ | |
| 203 | ||
| 204 | /* | |
| 205 | * FLASH related | |
| 206 | */ | |
| 207 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
| 208 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
| 209 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ | |
| 210 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ | |
| 211 | ||
| 212 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 213 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ | |
| 214 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ | |
| 215 | ||
| 216 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ | |
| 217 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ | |
| 218 | ||
| 219 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ | |
| 220 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ | |
| 221 | ||
| 222 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
| 223 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 224 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ | |
| 225 | ||
| 226 | /* Address and size of Redundant Environment Sector */ | |
| 227 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) | |
| 228 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 229 | ||
| 230 | /* | |
| 231 | * PCI stuff | |
| 232 | */ | |
| 233 | /* General PCI */ | |
| 234 | #define CONFIG_PCI /* include pci support */ | |
| 235 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 236 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 237 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
| 238 | #define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ | |
| 239 | ||
| 240 | /* Board-specific PCI */ | |
| 241 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ | |
| 242 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
| 243 | ||
| 244 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
| 245 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
| 246 | ||
| 247 | /* | |
| 248 | * Xilinx System ACE support | |
| 249 | */ | |
| 250 | #define CONFIG_SYSTEMACE /* Enable SystemACE support */ | |
| 251 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ | |
| 252 | #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE | |
| 253 | #define CONFIG_DOS_PARTITION | |
| 254 | ||
| 255 | /* | |
| 256 | * External Bus Controller (EBC) Setup | |
| 257 | */ | |
| 258 | ||
| 259 | /* Memory Bank 0 (Flash) initialization */ | |
| 260 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
| 261 | EBC_BXAP_TWT_ENCODE(7) | \ | |
| 262 | EBC_BXAP_BCE_DISABLE | \ | |
| 263 | EBC_BXAP_BCT_2TRANS | \ | |
| 264 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 265 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 266 | EBC_BXAP_WBN_ENCODE(0) | \ | |
| 267 | EBC_BXAP_WBF_ENCODE(0) | \ | |
| 268 | EBC_BXAP_TH_ENCODE(0) | \ | |
| 269 | EBC_BXAP_RE_DISABLED | \ | |
| 270 | EBC_BXAP_SOR_DELAYED | \ | |
| 271 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 272 | EBC_BXAP_PEN_DISABLED) | |
| 273 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ | |
| 274 | EBC_BXCR_BS_64MB | \ | |
| 275 | EBC_BXCR_BU_RW | \ | |
| 276 | EBC_BXCR_BW_16BIT) | |
| 277 | ||
| 278 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
| 279 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ | |
| 280 | EBC_BXAP_TWT_ENCODE(4) | \ | |
| 281 | EBC_BXAP_BCE_DISABLE | \ | |
| 282 | EBC_BXAP_BCT_2TRANS | \ | |
| 283 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 284 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 285 | EBC_BXAP_WBN_ENCODE(0) | \ | |
| 286 | EBC_BXAP_WBF_ENCODE(0) | \ | |
| 287 | EBC_BXAP_TH_ENCODE(0) | \ | |
| 288 | EBC_BXAP_RE_DISABLED | \ | |
| 289 | EBC_BXAP_SOR_NONDELAYED | \ | |
| 290 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 291 | EBC_BXAP_PEN_DISABLED) | |
| 292 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ | |
| 293 | EBC_BXCR_BS_1MB | \ | |
| 294 | EBC_BXCR_BU_RW | \ | |
| 295 | EBC_BXCR_BW_16BIT) | |
| 296 | ||
| 297 | /* | |
| 298 | * Initialize EBC CONFIG - | |
| 299 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
| 300 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
| 301 | */ | |
| 302 | #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ | |
| 303 | EBC_CFG_PTD_ENABLE | \ | |
| 304 | EBC_CFG_RTC_16PERCLK | \ | |
| 305 | EBC_CFG_ATC_PREVIOUS | \ | |
| 306 | EBC_CFG_DTC_PREVIOUS | \ | |
| 307 | EBC_CFG_CTC_PREVIOUS | \ | |
| 308 | EBC_CFG_OEO_PREVIOUS | \ | |
| 309 | EBC_CFG_EMC_DEFAULT | \ | |
| 310 | EBC_CFG_PME_DISABLE | \ | |
| 311 | EBC_CFG_PR_16) | |
| 312 | ||
| 313 | /* | |
| 314 | * GPIO Setup | |
| 315 | */ | |
| 316 | #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 | |
| 317 | #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 | |
| 318 | #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 | |
| 319 | #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 | |
| 320 | ||
| 321 | #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ | |
| 322 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ | |
| 323 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ | |
| 324 | GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) | |
| 325 | #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
| 326 | #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
| 327 | #define CONFIG_SYS_GPIO_ODR 0 | |
| 328 | ||
| 329 | #endif /* __CONFIG_H */ |