[people/ms/u-boot.git] / include / configs / igep00x0.h

/*
 * Common configuration settings for IGEP technology based boards
 *
 * (C) Copyright 2012
 * ISEE 2007 SL, <www.iseebcn.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __IGEP00X0_H
#define __IGEP00X0_H

#include <asm/sizes.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP_GPIO

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * NS16550 Configuration
 */

#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/* define to avoid U-Boot to hang while waiting for TEMT */
#define CONFIG_SYS_NS16550_BROKEN_TEMT

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"IGEP"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
#endif
#ifdef CONFIG_BOOT_NAND
#define CONFIG_CMD_NAND
#endif
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS		/* NFS support			*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
#define CONFIG_MTD_DEVICE

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1

#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"usbtty=cdc_acm\0" \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext4 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from onenand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loaduimage; then " \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \

#define CONFIG_AUTO_COMPLETE		1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"U-Boot # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*
 * Physical Memory Map
 *
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

#ifdef CONFIG_BOOT_ONENAND
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */

#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_ENV_IS_IN_ONENAND	1
#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
#endif

#ifdef CONFIG_BOOT_NAND
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BASE		NAND_BASE
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_NAND	        1
#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
#define CONFIG_SYS_MAX_NAND_DEVICE      1
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * SMSC911x Ethernet
 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	0x2C000000
#endif /* (CONFIG_CMD_NET) */

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

/* MMC boot config */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT

#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_SPL_ONENAND_SUPPORT

/* OneNAND boot config */
#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)

#endif

#ifdef CONFIG_BOOT_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#endif

#endif /* __IGEP00X0_H */
Commit	Line	Data
8a3f6bb6	1	/*
dc7a9e64 EBS	2	* Common configuration settings for IGEP technology based boards
	3	*
	4	* (C) Copyright 2012
8a3f6bb6 EBS	5	* ISEE 2007 SL, <www.iseebcn.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
dc7a9e64 EBS	23	#ifndef __IGEP00X0_H
	24	#define __IGEP00X0_H
	25
8a3f6bb6 EBS	26	#include <asm/sizes.h>
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
8a3f6bb6 EBS	31	#define CONFIG_OMAP 1 /* in a TI OMAP core */
8a3f6bb6 EBS	32	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
308252ad	33	#define CONFIG_OMAP_GPIO
8a3f6bb6 EBS	34
	35	#define CONFIG_SDRC /* The chip has SDRC controller */
	36
	37	#include <asm/arch/cpu.h>
	38	#include <asm/arch/omap3.h>
	39
	40	/*
	41	* Display CPU and Board information
	42	*/
	43	#define CONFIG_DISPLAY_CPUINFO 1
	44	#define CONFIG_DISPLAY_BOARDINFO 1
	45
	46	/* Clock Defines */
	47	#define V_OSCK 26000000 /* Clock output from T2 */
	48	#define V_SCLK (V_OSCK >> 1)
	49
	50	#define CONFIG_MISC_INIT_R
	51
	52	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	53	#define CONFIG_SETUP_MEMORY_TAGS 1
	54	#define CONFIG_INITRD_TAG 1
	55	#define CONFIG_REVISION_TAG 1
	56
2fa8ca98 GL	57	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	58
8a3f6bb6 EBS	59	/*
	60	* NS16550 Configuration
	61	*/
	62
	63	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	64
	65	#define CONFIG_SYS_NS16550
	66	#define CONFIG_SYS_NS16550_SERIAL
	67	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	68	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	69
039cbaef JMC	70	/* define to avoid U-Boot to hang while waiting for TEMT */
	71	#define CONFIG_SYS_NS16550_BROKEN_TEMT
	72
8a3f6bb6 EBS	73	/* select serial console configuration */
	74	#define CONFIG_CONS_INDEX 3
	75	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	76	#define CONFIG_SERIAL3 3
	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
	80	#define CONFIG_BAUDRATE 115200
dc7a9e64 EBS	81	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
dc7a9e64 EBS	82	115200}
f49d7b6c	83	#define CONFIG_GENERIC_MMC 1
8a3f6bb6	84	#define CONFIG_MMC 1
f49d7b6c	85	#define CONFIG_OMAP_HSMMC 1
8a3f6bb6 EBS	86	#define CONFIG_DOS_PARTITION 1
8a3f6bb6 EBS	87
8a3f6bb6 EBS	88	/* USB */
	89	#define CONFIG_MUSB_UDC 1
	90	#define CONFIG_USB_OMAP3 1
	91	#define CONFIG_TWL4030_USB 1
	92
	93	/* USB device configuration */
	94	#define CONFIG_USB_DEVICE 1
	95	#define CONFIG_USB_TTY 1
	96	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	97
	98	/* Change these to suit your needs */
	99	#define CONFIG_USBD_VENDORID 0x0451
	100	#define CONFIG_USBD_PRODUCTID 0x5678
	101	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	102	#define CONFIG_USBD_PRODUCT_NAME "IGEP"
	103
	104	/* commands to include */
	105	#include <config_cmd_default.h>
	106
	107	#define CONFIG_CMD_CACHE
	108	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	109	#define CONFIG_CMD_FAT /* FAT support */
	110	#define CONFIG_CMD_I2C /* I2C serial bus support */
	111	#define CONFIG_CMD_MMC /* MMC support */
ca511cfb	112	#ifdef CONFIG_BOOT_ONENAND
8a3f6bb6	113	#define CONFIG_CMD_ONENAND /* ONENAND support */
ca511cfb JMC	114	#endif
	115	#ifdef CONFIG_BOOT_NAND
	116	#define CONFIG_CMD_NAND
	117	#endif
77eea280	118	#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
8a3f6bb6	119	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
77eea280	120	#endif
8a3f6bb6 EBS	121	#define CONFIG_CMD_DHCP
	122	#define CONFIG_CMD_PING
	123	#define CONFIG_CMD_NFS /* NFS support */
	124	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	125	#define CONFIG_MTD_DEVICE
	126
	127	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	128	#undef CONFIG_CMD_IMLS /* List all found images */
	129
	130	#define CONFIG_SYS_NO_FLASH
	131	#define CONFIG_HARD_I2C 1
	132	#define CONFIG_SYS_I2C_SPEED 100000
	133	#define CONFIG_SYS_I2C_SLAVE 1
	134	#define CONFIG_SYS_I2C_BUS 0
	135	#define CONFIG_SYS_I2C_BUS_SELECT 1
	136	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	137
	138	/*
	139	* TWL4030
	140	*/
	141	#define CONFIG_TWL4030_POWER 1
	142
8a3f6bb6 EBS	143	#define CONFIG_BOOTDELAY 3
	144
	145	#define CONFIG_EXTRA_ENV_SETTINGS \
304a46ca EBS	146	"usbtty=cdc_acm\0" \
	147	"loadaddr=0x82000000\0" \
	148	"usbtty=cdc_acm\0" \
e5e73c17	149	"console=ttyO2,115200n8\0" \
f1e445c3	150	"mpurate=auto\0" \
304a46ca EBS	151	"vram=12M\0" \
	152	"dvimode=1024x768MR-16@60\0" \
	153	"defaultdisplay=dvi\0" \
	154	"mmcdev=0\0" \
	155	"mmcroot=/dev/mmcblk0p2 rw\0" \
b4ebeb86	156	"mmcrootfstype=ext4 rootwait\0" \
304a46ca EBS	157	"nandroot=/dev/mtdblock4 rw\0" \
	158	"nandrootfstype=jffs2\0" \
	159	"mmcargs=setenv bootargs console=${console} " \
	160	"mpurate=${mpurate} " \
	161	"vram=${vram} " \
	162	"omapfb.mode=dvi:${dvimode} " \
	163	"omapfb.debug=y " \
	164	"omapdss.def_disp=${defaultdisplay} " \
	165	"root=${mmcroot} " \
	166	"rootfstype=${mmcrootfstype}\0" \
	167	"nandargs=setenv bootargs console=${console} " \
	168	"mpurate=${mpurate} " \
	169	"vram=${vram} " \
	170	"omapfb.mode=dvi:${dvimode} " \
	171	"omapfb.debug=y " \
	172	"omapdss.def_disp=${defaultdisplay} " \
	173	"root=${nandroot} " \
	174	"rootfstype=${nandrootfstype}\0" \
1b8ec016 EBS	175	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
	176	"importbootenv=echo Importing environment from mmc ...; " \
	177	"env import -t $loadaddr $filesize\0" \
304a46ca EBS	178	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	179	"mmcboot=echo Booting from mmc ...; " \
	180	"run mmcargs; " \
	181	"bootm ${loadaddr}\0" \
	182	"nandboot=echo Booting from onenand ...; " \
	183	"run nandargs; " \
	184	"onenand read ${loadaddr} 280000 400000; " \
	185	"bootm ${loadaddr}\0" \
	186
	187	#define CONFIG_BOOTCOMMAND \
66968110	188	"mmc dev ${mmcdev}; if mmc rescan; then " \
1b8ec016 EBS	189	"echo SD/MMC found on device ${mmcdev};" \
	190	"if run loadbootenv; then " \
	191	"run importbootenv;" \
	192	"fi;" \
	193	"if test -n $uenvcmd; then " \
	194	"echo Running uenvcmd ...;" \
	195	"run uenvcmd;" \
	196	"fi;" \
	197	"if run loaduimage; then " \
	198	"run mmcboot;" \
	199	"fi;" \
	200	"fi;" \
	201	"run nandboot;" \
8a3f6bb6 EBS	202
	203	#define CONFIG_AUTO_COMPLETE 1
	204
	205	/*
	206	* Miscellaneous configurable options
	207	*/
	208	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	209	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
8a3f6bb6 EBS	210	#define CONFIG_SYS_PROMPT "U-Boot # "
	211	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	212	/* Print Buffer Size */
	213	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	214	sizeof(CONFIG_SYS_PROMPT) + 16)
	215	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	216	/* Boot Argument Buffer Size */
	217	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	218
	219	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	220	/* works on */
	221	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	222	0x01F00000) /* 31MB */
	223
	224	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	225	/* load address */
	226
	227	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	228
	229	/*
	230	* OMAP3 has 12 GP timers, they can be driven by the system clock
	231	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	232	* This rate is divided by a local divisor.
	233	*/
	234	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	235	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	236	#define CONFIG_SYS_HZ 1000
	237
8a3f6bb6 EBS	238	/*
	239	* Physical Memory Map
	240	*
	241	*/
	242	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	243	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
8a3f6bb6 EBS	244	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
8a3f6bb6 EBS	245
8a3f6bb6 EBS	246	/*
	247	* FLASH and environment organization
	248	*/
	249
ca511cfb	250	#ifdef CONFIG_BOOT_ONENAND
8a3f6bb6 EBS	251	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
	252
	253	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	254
	255	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	256
	257	#define CONFIG_ENV_IS_IN_ONENAND 1
	258	#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
	259	#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
ca511cfb JMC	260	#endif
	261
	262	#ifdef CONFIG_BOOT_NAND
	263	#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
	264	#define CONFIG_NAND_OMAP_GPMC
	265	#define CONFIG_SYS_NAND_BASE NAND_BASE
	266	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	267	#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
	268	#define CONFIG_ENV_IS_IN_NAND 1
	269	#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
	270	#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
	271	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	272	#endif
8a3f6bb6 EBS	273
	274	/*
	275	* Size of malloc() pool
	276	*/
	277	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
8a3f6bb6 EBS	278
	279	/*
	280	* SMSC911x Ethernet
	281	*/
	282	#if defined(CONFIG_CMD_NET)
8a3f6bb6 EBS	283	#define CONFIG_SMC911X
	284	#define CONFIG_SMC911X_32_BIT
	285	#define CONFIG_SMC911X_BASE 0x2C000000
	286	#endif /* (CONFIG_CMD_NET) */
	287
d271a611 JMC	288	/*
	289	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	290	* and older u-boot.bin with the new U-Boot SPL.
	291	*/
	292	#define CONFIG_SYS_TEXT_BASE 0x80008000
8a3f6bb6	293	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	294	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	295	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	296	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	297	CONFIG_SYS_INIT_RAM_SIZE - \
	298	GENERATED_GBL_DATA_SIZE)
8a3f6bb6	299
d271a611 JMC	300	/* SPL */
d271a611 JMC	301	#define CONFIG_SPL
47f7bcae	302	#define CONFIG_SPL_FRAMEWORK
d271a611 JMC	303	#define CONFIG_SPL_NAND_SIMPLE
	304	#define CONFIG_SPL_TEXT_BASE 0x40200800
	305	#define CONFIG_SPL_MAX_SIZE (54 * 1024)
	306	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	307
	308	/* move malloc and bss high to prevent clashing with the main image */
	309	#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
	310	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	311	#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
	312	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	313
	314	/* MMC boot config */
	315	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	316	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	317	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	318	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	319
0e29a248	320	#define CONFIG_SPL_BOARD_INIT
d271a611 JMC	321	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	322	#define CONFIG_SPL_LIBDISK_SUPPORT
	323	#define CONFIG_SPL_I2C_SUPPORT
	324	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	325	#define CONFIG_SPL_MMC_SUPPORT
	326	#define CONFIG_SPL_FAT_SUPPORT
	327	#define CONFIG_SPL_SERIAL_SUPPORT
	328
	329	#define CONFIG_SPL_POWER_SUPPORT
	330	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	331
	332	#ifdef CONFIG_BOOT_ONENAND
	333	#define CONFIG_SPL_ONENAND_SUPPORT
	334
	335	/* OneNAND boot config */
	336	#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
	337	#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
	338	#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
	339	#define CONFIG_SPL_ONENAND_LOAD_SIZE \
	340	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
	341
	342	#endif
	343
	344	#ifdef CONFIG_BOOT_NAND
	345	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	346	#define CONFIG_SPL_NAND_BASE
	347	#define CONFIG_SPL_NAND_DRIVERS
	348	#define CONFIG_SPL_NAND_ECC
d271a611 JMC	349
	350	/* NAND boot config */
	351	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	352	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	353	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	354	#define CONFIG_SYS_NAND_OOBSIZE 64
	355	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	356	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	357	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	358	10, 11, 12, 13}
	359	#define CONFIG_SYS_NAND_ECCSIZE 512
	360	#define CONFIG_SYS_NAND_ECCBYTES 3
	361	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	362	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	363	#endif
	364
dc7a9e64	365	#endif /* __IGEP00X0_H */