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Convert CONFIG_CMD_EEPROM et al to Kconfig
[people/ms/u-boot.git] / include / configs / imx31_phycore.h
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1/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
7064122c 7 * Configuration settings for the phyCORE-i.MX31 board.
5ad86216 8 *
3765b3e7 9 * SPDX-License-Identifier: GPL-2.0+
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10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
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15#include <asm/arch/imx-regs.h>
16
6ac1c903 17/* High Level Configuration Options */
3fd968e9 18#define CONFIG_MX31 /* This is a mx31 */
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19#define CONFIG_MX31_CLK32 32000
20
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21#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22#define CONFIG_SETUP_MEMORY_TAGS
23#define CONFIG_INITRD_TAG
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24
25/*
26 * Size of malloc() pool
27 */
62a22dca 28#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
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29
30/*
31 * Hardware drivers
32 */
33
b089d039 34#define CONFIG_SYS_I2C
35#define CONFIG_SYS_I2C_MXC
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36#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
37#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 38#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
de6f604d 39#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
5ad86216 40
6ac1c903 41#define CONFIG_MXC_UART
40f6fffe 42#define CONFIG_MXC_UART_BASE UART1_BASE
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43
44/* allow to overwrite serial and ethaddr */
45#define CONFIG_ENV_OVERWRITE
46#define CONFIG_CONS_INDEX 1
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47
48/***********************************************************
49 * Command definition
50 ***********************************************************/
5ad86216 51
5ad86216 52
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53#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
54 "1536k(kernel),-(root)"
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55
56#define CONFIG_NETMASK 255.255.255.0
57#define CONFIG_IPADDR 192.168.23.168
58#define CONFIG_SERVERIP 192.168.23.2
59
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60#define CONFIG_EXTRA_ENV_SETTINGS \
61 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
62 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
63 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
64 "bootargs_flash=setenv bootargs $(bootargs) " \
65 "root=/dev/mtdblock2 rootfstype=jffs2\0" \
66 "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
67 "bootcmd=run bootcmd_net\0" \
68 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
69 "tftpboot 0x80000000 $(uimage);bootm\0" \
70 "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
71 "bootm 0x80000000\0" \
72 "unlock=yes\0" \
73 "mtdparts=" MTDPARTS_DEFAULT "\0" \
74 "prg_uboot=tftpboot 0x80000000 $(uboot);" \
75 "protect off 0xa0000000 +0x20000;" \
76 "erase 0xa0000000 +0x20000;" \
77 "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
78 "prg_kernel=tftpboot 0x80000000 $(uimage);" \
79 "erase 0xa0040000 +0x180000;" \
80 "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
81 "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
82 "erase 0xa01c0000 0xa1ffffff;" \
83 "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
84 "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
85 "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
86 "sync:1241513985,vmode:0\0"
87
6ac1c903 88#define CONFIG_SMC911X
736fead8 89#define CONFIG_SMC911X_BASE 0xa8000000
6ac1c903 90#define CONFIG_SMC911X_32_BIT
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91
92/*
93 * Miscellaneous configurable options
94 */
6d0f6bcf 95#define CONFIG_SYS_LONGHELP /* undef to save memory */
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96/* Console I/O Buffer Size */
97#define CONFIG_SYS_CBSIZE 256
5ad86216 98/* Print Buffer Size */
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99#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
100 sizeof(CONFIG_SYS_PROMPT) + 16)
101/* max number of command args */
102#define CONFIG_SYS_MAXARGS 16
103/* Boot Argument Buffer Size */
104#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5ad86216 105
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106#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
107#define CONFIG_SYS_MEMTEST_END 0x10000
5ad86216 108
6d0f6bcf 109#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
5ad86216 110
6ac1c903 111#define CONFIG_CMDLINE_EDITING
5ad86216 112
6ac1c903 113/*
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114 * Physical Memory Map
115 */
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116#define CONFIG_NR_DRAM_BANKS 1
117#define PHYS_SDRAM_1 0x80000000
118#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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119#define CONFIG_SYS_TEXT_BASE 0xA0000000
120
121#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
122#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
123#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
124#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
125 GENERATED_GBL_DATA_SIZE)
126#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
127 CONFIG_SYS_GBL_DATA_OFFSET)
5ad86216 128
6ac1c903 129/*
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130 * FLASH and environment organization
131 */
6d0f6bcf 132#define CONFIG_SYS_FLASH_BASE 0xa0000000
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133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
135/* Monitor at beginning of flash */
136#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
137
138#define CONFIG_ENV_IS_IN_EEPROM
139#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
140#define CONFIG_ENV_SIZE 4096
6d0f6bcf 141#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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142#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
143#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
144#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
5ad86216 145
6ac1c903 146/*
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147 * CFI FLASH driver setup
148 */
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149#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
150#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
151#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
152#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
5ad86216 153
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154/*
155 * Timeout for Flash Erase and Flash Write
156 * timeout values are in ticks
157 */
158#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
159#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
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160
161/*
162 * JFFS2 partitions
163 */
68d7d651 164#undef CONFIG_CMD_MTDPARTS
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165#define CONFIG_JFFS2_DEV "nor0"
166
a2bb7105 167/* EET platform additions */
f428268a 168#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
c4ea1424 169#define CONFIG_MXC_GPIO
a2bb7105 170
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171#define CONFIG_HARD_SPI
172#define CONFIG_MXC_SPI
a2bb7105 173
6ac1c903 174#define CONFIG_S6E63D6
a2bb7105 175
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176#define CONFIG_VIDEO_MX3
177#define CONFIG_VIDEO_LOGO
62a22dca 178#define CONFIG_SPLASH_SCREEN
62a22dca 179#define CONFIG_BMP_16BPP
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180#endif
181
5ad86216 182#endif /* __CONFIG_H */