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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments. | |
4 | * Kshitij Gupta <kshitij@ti.com> | |
5 | * Configuation settings for the TI OMAP Innovator board. | |
6 | * | |
7 | * (C) Copyright 2004 | |
8 | * ARM Ltd. | |
9 | * Philippe Robin, <philippe.robin@arm.com> | |
10 | * Configuration for Compact Integrator board. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
7c0e483d | 34 | /* Integrator-specific configuration */ |
23b3ae0f | 35 | #define CONFIG_INTEGRATOR |
7c0e483d LW |
36 | #define CONFIG_ARCH_CINTEGRATOR |
37 | #define CONFIG_CM_INIT | |
38 | #define CONFIG_CM_REMAP | |
39 | #define CONFIG_CM_SPD_DETECT | |
40 | ||
3d3befa7 WD |
41 | /* |
42 | * High Level Configuration Options | |
43 | * (easy to change) | |
44 | */ | |
a4c15c01 | 45 | #define CONFIG_SYS_TEXT_BASE 0x01000000 |
6d0f6bcf JCPV |
46 | #define CONFIG_SYS_MEMTEST_START 0x100000 |
47 | #define CONFIG_SYS_MEMTEST_END 0x10000000 | |
48 | #define CONFIG_SYS_HZ 1000 | |
49 | #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ | |
50 | #define CONFIG_SYS_TIMERBASE 0x13000100 | |
3d3befa7 | 51 | |
74f4304e | 52 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
3d3befa7 | 53 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
74f4304e | 54 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ |
7c0e483d | 55 | |
3d3befa7 WD |
56 | /* |
57 | * Size of malloc() pool | |
58 | */ | |
6d0f6bcf | 59 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
3d3befa7 WD |
60 | |
61 | /* | |
62 | * Hardware drivers | |
63 | */ | |
7194ab80 | 64 | #define CONFIG_SMC91111 |
3d3befa7 WD |
65 | #define CONFIG_SMC_USE_32_BIT |
66 | #define CONFIG_SMC91111_BASE 0xC8000000 | |
67 | #undef CONFIG_SMC91111_EXT_PHY | |
68 | ||
69 | /* | |
70 | * NS16550 Configuration | |
71 | */ | |
48d0192f | 72 | #define CONFIG_PL011_SERIAL |
6705d81e | 73 | #define CONFIG_PL011_CLOCK 14745600 |
6d0f6bcf | 74 | #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 } |
3d3befa7 | 75 | #define CONFIG_CONS_INDEX 0 |
5a95f6fb | 76 | #define CONFIG_BAUDRATE 38400 |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_SERIAL0 0x16000000 |
78 | #define CONFIG_SYS_SERIAL1 0x17000000 | |
3d3befa7 | 79 | |
1d2c6bc4 | 80 | |
079a136c JL |
81 | /* |
82 | * BOOTP options | |
83 | */ | |
84 | #define CONFIG_BOOTP_BOOTFILESIZE | |
85 | #define CONFIG_BOOTP_BOOTPATH | |
86 | #define CONFIG_BOOTP_GATEWAY | |
87 | #define CONFIG_BOOTP_HOSTNAME | |
88 | ||
89 | ||
5a95f6fb | 90 | /* |
1d2c6bc4 JL |
91 | * Command line configuration. |
92 | */ | |
7c0e483d | 93 | #include <config_cmd_default.h> |
3d3befa7 | 94 | |
3d3befa7 | 95 | #define CONFIG_BOOTDELAY 2 |
7c0e483d LW |
96 | #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" |
97 | #define CONFIG_BOOTCOMMAND "tftpboot ; bootm" | |
98 | #define CONFIG_SERVERIP 192.168.1.100 | |
99 | #define CONFIG_IPADDR 192.168.1.104 | |
100 | #define CONFIG_BOOTFILE "uImage" | |
74f4304e | 101 | |
3d3befa7 WD |
102 | /* |
103 | * Miscellaneous configurable options | |
104 | */ | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
106 | #define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ | |
107 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ | |
3d3befa7 | 108 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
110 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
111 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ | |
3d3befa7 | 112 | |
6d0f6bcf | 113 | #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ |
3d3befa7 | 114 | |
3d3befa7 WD |
115 | /*----------------------------------------------------------------------- |
116 | * Physical Memory Map | |
117 | */ | |
9b880bd4 WD |
118 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
119 | #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ | |
53677ef1 | 120 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
9ecefbfe LW |
121 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
122 | #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE | |
123 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ | |
124 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
125 | GENERATED_GBL_DATA_SIZE) | |
126 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET | |
3d3befa7 WD |
127 | |
128 | /*----------------------------------------------------------------------- | |
129 | * FLASH and environment organization | |
9b880bd4 WD |
130 | |
131 | * Top varies according to amount fitted | |
132 | * Reserve top 4 blocks of flash | |
133 | * - ARM Boot Monitor | |
134 | * - Unused | |
135 | * - SIB block | |
136 | * - U-Boot environment | |
137 | * | |
138 | * Base is always 0x24000000 | |
139 | ||
3d3befa7 | 140 | */ |
6d0f6bcf | 141 | #define CONFIG_SYS_FLASH_BASE 0x24000000 |
46937b27 JCPV |
142 | #define CONFIG_SYS_FLASH_CFI 1 |
143 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_MAX_FLASH_SECT 64 |
145 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
46937b27 | 146 | #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
148 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
3d3befa7 | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_MONITOR_LEN 0x00100000 |
5a1aceb0 | 151 | #define CONFIG_ENV_IS_IN_FLASH 1 |
9b880bd4 WD |
152 | |
153 | /* | |
154 | * Move up the U-Boot & monitor area if more flash is fitted. | |
155 | * If this U-Boot is to be run on Integrators with varying flash sizes, | |
7817cb20 | 156 | * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG |
6d0f6bcf JCPV |
157 | * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE |
158 | * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not | |
9b880bd4 WD |
159 | * embedded in the boot monitor(s) area |
160 | */ | |
161 | #if ( PHYS_FLASH_SIZE == 0x04000000 ) | |
162 | ||
0e8d1586 | 163 | #define CONFIG_ENV_ADDR 0x27F00000 |
6d0f6bcf | 164 | #define CONFIG_SYS_MONITOR_BASE 0x27F40000 |
9b880bd4 WD |
165 | |
166 | #elif (PHYS_FLASH_SIZE == 0x02000000 ) | |
167 | ||
0e8d1586 | 168 | #define CONFIG_ENV_ADDR 0x25F00000 |
6d0f6bcf | 169 | #define CONFIG_SYS_MONITOR_BASE 0x25F40000 |
9b880bd4 WD |
170 | |
171 | #else | |
172 | ||
0e8d1586 | 173 | #define CONFIG_ENV_ADDR 0x24F00000 |
6d0f6bcf | 174 | #define CONFIG_SYS_MONITOR_BASE 0x27F40000 |
9b880bd4 WD |
175 | |
176 | #endif | |
177 | ||
0e8d1586 JCPV |
178 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ |
179 | #define CONFIG_ENV_SIZE 8192 /* 8KB */ | |
9b880bd4 WD |
180 | |
181 | /* | |
182 | * The ARM boot monitor initializes the board. | |
183 | * However, the default U-Boot code also performs the initialization. | |
184 | * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT | |
185 | * - see documentation supplied with board for details of how to choose the | |
186 | * image to run at reset/power up | |
187 | * e.g. whether the ARM Boot Monitor runs before U-Boot | |
5a95f6fb | 188 | |
9b880bd4 WD |
189 | #define CONFIG_SKIP_LOWLEVEL_INIT |
190 | ||
191 | */ | |
192 | ||
193 | /* | |
194 | * The ARM boot monitor does not relocate U-Boot. | |
195 | * However, the default U-Boot code performs the relocation check, | |
196 | * and may relocate the code if the memory map is changed. | |
197 | * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT | |
198 | ||
199 | #define SKIP_CONFIG_RELOCATE_UBOOT | |
200 | ||
201 | */ | |
74f4304e WD |
202 | /*----------------------------------------------------------------------- |
203 | * There are various dependencies on the core module (CM) fitted | |
204 | * Users should refer to their CM user guide | |
205 | * - when porting adjust u-boot/Makefile accordingly | |
9b880bd4 WD |
206 | * to define the necessary CONFIG_ s for the CM involved |
207 | * see e.g. cp_926ejs_config | |
74f4304e WD |
208 | */ |
209 | ||
9b880bd4 | 210 | #include "armcoremodule.h" |
74f4304e | 211 | |
9b880bd4 WD |
212 | /* |
213 | * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & | |
214 | * the core module has a CM_INIT register | |
215 | * then the U-Boot initialisation code will | |
216 | * e.g. ARM Boot Monitor or pre-loader is repeated once | |
217 | * (to re-initialise any existing CM_INIT settings to safe values). | |
218 | * | |
219 | * This is usually not the desired behaviour since the platform | |
220 | * will either reboot into the ARM monitor (or pre-loader) | |
221 | * or continuously cycle thru it without U-Boot running, | |
222 | * depending upon the setting of Integrator/CP switch S2-4. | |
223 | * | |
224 | * However it may be needed if Integrator/CP switch S2-1 | |
225 | * is set OFF to boot direct into U-Boot. | |
226 | * In that case comment out the line below. | |
227 | #undef CONFIG_CM_INIT | |
228 | */ | |
74f4304e | 229 | |
5a95f6fb | 230 | #endif /* __CONFIG_H */ |