[people/ms/u-boot.git] / include / configs / intip.h

/*
 * (C) Copyright 2009
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * Based on include/configs/canyonlands.h
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
/*
 * This config file is used for CompactCenter(codename intip) and DevCon-Center
 */
#define CONFIG_460EX		1	/* Specific PPC460EX		*/
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_HOSTNAME		devconcenter
#define CONFIG_IDENT_STRING	" devconcenter 0.06"
#else
#define CONFIG_HOSTNAME		intip
#define CONFIG_IDENT_STRING	" intip 0.06"
#endif
#define CONFIG_440		1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
#endif

/*
 * Include common defines/options for all AMCC eval boards
 */
#include "amcc-common.h"

#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_TYPES		1	/* support board types */
#define CONFIG_FIT
#define CFG_ALT_MEMTEST

#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory */
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE

/* EBC stuff */
#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* later mapped here */
#define CONFIG_SYS_FLASH_SIZE		(128 << 20)
#else
#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped here */
#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
#endif

#define CONFIG_SYS_NVRAM_BASE		0xE0000000
#define CONFIG_SYS_UART_BASE		0xE0100000
#define CONFIG_SYS_IO_BASE		0xE0200000

#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xC8000000
#else
#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
#endif
#define CONFIG_SYS_FLASH_BASE_PHYS \
	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
	| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)

#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k */
#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000

#define CONFIG_SYS_AHB_BASE		0xE2000000	/* int. AHB periph. */

/*
 * Initial RAM & stack pointer (placed in OCM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/

/*
 * Environment
 */
/*
 * Define here the location of the environment variables (FLASH).
 */
#define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */

/*
 * FLASH related
 */
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD reset cmd */

#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#ifdef CONFIG_DEVCONCENTER
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max num of sectors per chip*/
#else
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
#endif

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buff'd writes (20x faster) */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*
 * DDR SDRAM
 */

#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */

#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A

/* DDR1/2 SDRAM Device Control Register Data Values */
/* Memory Queue */
#define CONFIG_SYS_SDRAM_R0BAS		0x0000f800
#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
#define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000

/* SDRAM Controller */
#define CONFIG_SYS_SDRAM0_MB0CF		0x00000201
#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
#define CONFIG_SYS_SDRAM0_MCOPT1	0x05120000
#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
#define CONFIG_SYS_SDRAM0_MODT0		0x00000000
#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
#define CONFIG_SYS_SDRAM0_CODT		0x00000020
#define CONFIG_SYS_SDRAM0_RTR		0x06180000
#define CONFIG_SYS_SDRAM0_INITPLR0	0xA8380000
#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000552
#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
#define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR8	0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000452
#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
#define CONFIG_SYS_SDRAM0_DLCR		0x00000000
#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
#define CONFIG_SYS_SDRAM0_WRDTR		0x86000823
#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
#define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
#define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
#define CONFIG_SYS_SDRAM0_MMODE		0x00000452
#define CONFIG_SYS_SDRAM0_MEMODE	0x00000002

#define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */

/*
 * I2C
 */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/* I2C bootstrap EEPROM */
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
#define CONFIG_4xx_CONFIG_BLOCKSIZE		16

/* I2C SYSMON */
#define CONFIG_DTT_LM63         1       /* National LM63        */
#define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
#define CONFIG_DTT_PWM_LOOKUPTABLE      \
	{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT   0xa10

/* RTC configuration */
#define CONFIG_RTC_DS1337	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/*
 * Ethernet
 */
#define CONFIG_IBM_EMAC4_V4	1

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1

#define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR	3

#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_PHY_DYNAMIC_ANEG	1

/*
 * USB-OHCI
 */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#undef CONFIG_SYS_OHCI_BE_CONTROLLER	/* 460EX has little endian descriptors*/
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register */
#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode */
#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15

/*
 * Default environment variables
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	"pciconfighost=1\0"						\
	"pcie_mode=RP:RP\0"						\
	""

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * PCI stuff
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_PCI_DISABLE_PCIE

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT	/* let board init pci target */
#undef	CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */


/*
 * External Bus Controller (EBC) Setup
 */

/*
 * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 * boot EBC mapping only supports a maximum of 16MBytes
 * (4.ff00.0000 - 4.ffff.ffff).
 * To solve this problem, the FLASH has to get remapped to another
 * EBC address which accepts bigger regions:
 *
 * 0xfc00.0000 -> 4.cc00.0000
 */


/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP		0x10055e00
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)

/* Memory Bank 1 (NVRAM) initialization	*/
#define CONFIG_SYS_EBC_PB1AP		0x02815480
/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NVRAM_BASE | 0x18000)

/* Memory Bank 2 (UART) initialization	*/
#define CONFIG_SYS_EBC_PB2AP		0x02815480
/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_UART_BASE | 0x1A000)

/* Memory Bank 3 (IO) initialization */
#define CONFIG_SYS_EBC_PB3AP		0x02815480
/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_IO_BASE | 0x1A000)

/*
 * PPC4xx GPIO Configuration
 */
/* 460EX: Use USB configuration */
#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
{											\
/* GPIO Core 0 */									\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
},											\
{											\
/* GPIO Core 1 */									\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  USB_SERVICE_SUSPEND_N		*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51  SPI_CSS_N			*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52  FPGA_PROGRAM_UC_N		*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  FPGA_INIT_UC_N		*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54  WD_STROBE			*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  LED_2_OUT			*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56  LED_1_OUT			*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61  STARTUP_FINISHED_N		*/	\
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62  STARTUP_FINISHED		*/	\
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  SERVICE_PORT_ACTIVE		*/	\
}											\
}

#endif	/* __CONFIG_H */
Commit	Line	Data
ab4c62c1 DE	1	/*
	2	* (C) Copyright 2009
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
	5	* Based on include/configs/canyonlands.h
	6	* (C) Copyright 2008
	7	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
ab4c62c1 DE	10	*/
	11
	12	/*
4c188367	13	* intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
ab4c62c1 DE	14	*/
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* High Level Configuration Options
	20	*/
	21	/*
4c188367	22	* This config file is used for CompactCenter(codename intip) and DevCon-Center
ab4c62c1 DE	23	*/
	24	#define CONFIG_460EX 1 /* Specific PPC460EX */
	25	#ifdef CONFIG_DEVCONCENTER
	26	#define CONFIG_HOSTNAME devconcenter
996d88d8	27	#define CONFIG_IDENT_STRING " devconcenter 0.06"
ab4c62c1	28	#else
4c188367	29	#define CONFIG_HOSTNAME intip
996d88d8	30	#define CONFIG_IDENT_STRING " intip 0.06"
ab4c62c1 DE	31	#endif
ab4c62c1 DE	32	#define CONFIG_440 1
ab4c62c1	33
2ae18241 WD	34	#ifndef CONFIG_SYS_TEXT_BASE
	35	#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
	36	#endif
	37
ab4c62c1 DE	38	/*
	39	* Include common defines/options for all AMCC eval boards
	40	*/
	41	#include "amcc-common.h"
	42
	43	#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
	44
	45	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	46	#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
	47	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
d9f923ff	48	#define CONFIG_SYS_GENERIC_BOARD
ab4c62c1 DE	49	#define CONFIG_BOARD_TYPES 1 /* support board types */
	50	#define CONFIG_FIT
	51	#define CFG_ALT_MEMTEST
	52
55ac719d	53	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
55ac719d	54
ab4c62c1 DE	55	/*
	56	* Base addresses -- Note these are effective addresses where the
	57	* actual resources get mapped (not physical addresses)
	58	*/
	59	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
	60	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	61	#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
	62
	63	/* EBC stuff */
	64	#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
	65	#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */
	66	#define CONFIG_SYS_FLASH_SIZE (128 << 20)
	67	#else
	68	#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
	69	#define CONFIG_SYS_FLASH_SIZE (64 << 20)
	70	#endif
	71
	72	#define CONFIG_SYS_NVRAM_BASE 0xE0000000
	73	#define CONFIG_SYS_UART_BASE 0xE0100000
	74	#define CONFIG_SYS_IO_BASE 0xE0200000
	75
	76	#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
	77	#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
	78	#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
	79	#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
	80	#else
	81	#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
	82	#endif
	83	#define CONFIG_SYS_FLASH_BASE_PHYS \
	84	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
	85	\| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
	86
	87	#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
	88	#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
bf560807	89	#define CONFIG_SYS_SRAM_SIZE (256 << 10)
ab4c62c1 DE	90	#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
ab4c62c1 DE	91
ab4c62c1 DE	92	#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
	93
	94	/*
	95	* Initial RAM & stack pointer (placed in OCM)
	96	*/
	97	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
553f0982	98	#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
ab4c62c1	99	#define CONFIG_SYS_GBL_DATA_OFFSET \
25ddd1fb	100	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
ab4c62c1 DE	101	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	102
	103	/*
	104	* Serial Port
	105	*/
550650dd	106	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
ab4c62c1 DE	107
	108	/*
	109	* Environment
	110	*/
	111	/*
	112	* Define here the location of the environment variables (FLASH).
	113	*/
	114	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	115	#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
	116
	117	/*
	118	* FLASH related
	119	*/
	120	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	121	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	122	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
	123
	124	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	125	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	126	#ifdef CONFIG_DEVCONCENTER
	127	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/
	128	#else
	129	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
	130	#endif
	131
	132	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
	133	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
	134
	135	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */
	136	#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
	137
	138	#ifdef CONFIG_ENV_IS_IN_FLASH
	139	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
	140	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	141	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	142
	143	/* Address and size of Redundant Environment Sector */
	144	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
	145	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	146	#endif /* CONFIG_ENV_IS_IN_FLASH */
	147
	148	/*
	149	* DDR SDRAM
	150	*/
	151
	152	#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
	153
	154	#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
	155	#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
	156	#undef CONFIG_PPC4xx_DDR_METHOD_A
	157
	158	/* DDR1/2 SDRAM Device Control Register Data Values */
	159	/* Memory Queue */
	160	#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
	161	#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
	162	#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
	163	#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
	164	#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
	165	#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
91d59904	166	#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
ab4c62c1 DE	167	#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
	168	#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
	169
	170	/* SDRAM Controller */
	171	#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
	172	#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
	173	#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
	174	#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
91d59904	175	#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000
ab4c62c1 DE	176	#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
	177	#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
	178	#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
	179	#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
	180	#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
	181	#define CONFIG_SYS_SDRAM0_CODT 0x00000020
	182	#define CONFIG_SYS_SDRAM0_RTR 0x06180000
	183	#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
	184	#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
	185	#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
	186	#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
91d59904	187	#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
15cc385e	188	#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
ab4c62c1 DE	189	#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
	190	#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
	191	#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
	192	#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
	193	#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
15cc385e	194	#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
91d59904 DE	195	#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
91d59904 DE	196	#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
ab4c62c1 DE	197	#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
	198	#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
	199	#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
91d59904 DE	200	#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
91d59904 DE	201	#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
ab4c62c1 DE	202	#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
ab4c62c1 DE	203	#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
15cc385e	204	#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
ab4c62c1 DE	205	#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
ab4c62c1 DE	206	#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
91d59904	207	#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
15cc385e	208	#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
91d59904	209	#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
ab4c62c1 DE	210
	211	#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
	212
	213	/*
	214	* I2C
	215	*/
880540de	216	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
ab4c62c1 DE	217
	218	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	219	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	220	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	221	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	222	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	223
	224	/* I2C bootstrap EEPROM */
	225	#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
	226	#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
	227	#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
	228
	229	/* I2C SYSMON */
	230	#define CONFIG_DTT_LM63 1 /* National LM63 */
	231	#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
	232	#define CONFIG_DTT_PWM_LOOKUPTABLE \
	233	{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
	234	#define CONFIG_DTT_TACH_LIMIT 0xa10
	235
	236	/* RTC configuration */
	237	#define CONFIG_RTC_DS1337 1
	238	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	239
	240	/*
	241	* Ethernet
	242	*/
	243	#define CONFIG_IBM_EMAC4_V4 1
	244
	245	#define CONFIG_HAS_ETH0
	246	#define CONFIG_HAS_ETH1
	247
	248	#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
	249	#define CONFIG_PHY1_ADDR 3
	250
	251	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	252	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	253	#define CONFIG_PHY_DYNAMIC_ANEG 1
	254
	255	/*
	256	* USB-OHCI
	257	*/
	258	#define CONFIG_USB_OHCI_NEW
	259	#define CONFIG_USB_STORAGE
	260	#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/
	261	#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
	262	#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
	263	#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE \| 0xd0000)
	264	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
	265	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	266
	267	/*
	268	* Default environment variables
	269	*/
	270	#define CONFIG_EXTRA_ENV_SETTINGS \
	271	CONFIG_AMCC_DEF_ENV \
	272	CONFIG_AMCC_DEF_ENV_POWERPC \
	273	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	274	"kernel_addr=fc000000\0" \
	275	"fdt_addr=fc1e0000\0" \
	276	"ramdisk_addr=fc200000\0" \
	277	"pciconfighost=1\0" \
	278	"pcie_mode=RP:RP\0" \
	279	""
	280
281	/*
282	* Commands additional to the ones defined in amcc-common.h
283	*/
284	#define CONFIG_CMD_CHIP_CONFIG
285	#define CONFIG_CMD_DATE
286	#define CONFIG_CMD_DTT
287	#define CONFIG_CMD_EXT2
288	#define CONFIG_CMD_FAT
289	#define CONFIG_CMD_PCI
290	#define CONFIG_CMD_SDRAM
291	#define CONFIG_CMD_SNTP
292	#define CONFIG_CMD_USB
293
294	/* Partitions */
295	#define CONFIG_MAC_PARTITION
296	#define CONFIG_DOS_PARTITION
297	#define CONFIG_ISO_PARTITION
298
299	/*
300	* PCI stuff
301	*/
302	/* General PCI */
303	#define CONFIG_PCI /* include pci support */
842033e6	304	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
ab4c62c1 DE	305	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	306	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	307	#define CONFIG_PCI_CONFIG_HOST_BRIDGE
	308	#define CONFIG_PCI_DISABLE_PCIE
	309
	310	/* Board-specific PCI */
	311	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
	312	#undef CONFIG_SYS_PCI_MASTER_INIT
	313
	314	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
	315	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	316
	317
	318	/*
	319	* External Bus Controller (EBC) Setup
	320	*/
	321
	322	/*
	323	* CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	324	* boot EBC mapping only supports a maximum of 16MBytes
	325	* (4.ff00.0000 - 4.ffff.ffff).
	326	* To solve this problem, the FLASH has to get remapped to another
	327	* EBC address which accepts bigger regions:
	328	*
	329	* 0xfc00.0000 -> 4.cc00.0000
	330	*/
	331
	332
	333	/* Memory Bank 0 (NOR-FLASH) initialization */
	334	#define CONFIG_SYS_EBC_PB0AP 0x10055e00
	335	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR \| 0x9a000)
	336
	337	/* Memory Bank 1 (NVRAM) initialization */
	338	#define CONFIG_SYS_EBC_PB1AP 0x02815480
	339	/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
	340	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE \| 0x18000)
	341
	342	/* Memory Bank 2 (UART) initialization */
	343	#define CONFIG_SYS_EBC_PB2AP 0x02815480
	344	/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
	345	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE \| 0x1A000)
	346
	347	/* Memory Bank 3 (IO) initialization */
	348	#define CONFIG_SYS_EBC_PB3AP 0x02815480
	349	/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
	350	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE \| 0x1A000)
	351
	352	/*
	353	* PPC4xx GPIO Configuration
	354	*/
	355	/* 460EX: Use USB configuration */
	356	#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
	357	{ \
	358	/* GPIO Core 0 */ \
	359	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
	360	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
	361	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
	362	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
	363	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
	364	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
	365	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
	366	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
	367	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
	368	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
369	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
370	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
371	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
372	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
373	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
374	{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
375	{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
376	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
377	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
378	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
379	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
380	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
381	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
382	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
383	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
384	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
385	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
386	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
387	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
388	{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
389	{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
390	{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
391	}, \
392	{ \
393	/* GPIO Core 1 */ \
394	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
395	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
396	{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
397	{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
398	{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
399	{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
400	{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
401	{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
402	{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
403	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
404	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
405	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
406	{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
407	{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
408	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
409	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
410	{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
411	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
412	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \
413	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \
414	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \
415	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \
416	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \
417	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \
418	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \
419	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
420	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
421	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
422	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
423	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \
424	{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \
425	{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \
426	} \
427	}
428
429	#endif /* __CONFIG_H */