[people/ms/u-boot.git] / include / configs / io.h

/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_405EP		1	/* this is a PPC405 CPU */
#define CONFIG_IO	        1	/*  on a Io board */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		io
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT

#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */

/*
 * Configure PLL
 */
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66

/* new uImage format support */
#define CONFIG_FIT_DISABLE_SHA256

#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	""

#define CONFIG_PHY_ADDR		4	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IRQ

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */

/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		691200

/*
 * I2C stuff
 */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000

/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63		1	/* National LM63	*/
#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
#define CONFIG_DTT_PWM_LOOKUPTABLE	\
		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT	0xa10

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */

#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/* Gbit PHYs */
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI

#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	/* our MDIO is GPIO0 */
#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	/* our MDC  is GPIO7 */

#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy"

/*
 * PPC405 GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
} \
}

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP		0xa382a880
/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000

/* Memory Bank 1 (NVRAM) initializatio */
#define CONFIG_SYS_EBC_PB1AP		0x92015480
/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
#define CONFIG_SYS_EBC_PB1CR		0x7f318000

/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_FPGA0_BASE		0x7f100000
#define CONFIG_SYS_EBC_PB2AP		0x02025080
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB2CR		0x7f11a000

#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k)		0x0010

#define CONFIG_SYS_FPGA_COUNT		1

#define CONFIG_SYS_FPGA_PTR \
	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }

#define CONFIG_SYS_FPGA_COMMON

/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE		0x7f200000
#define CONFIG_SYS_EBC_PB3AP		0xa2015480
/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB3CR		0x7f21a000

#define CONFIG_SYS_LATCH0_RESET		0xffff
#define CONFIG_SYS_LATCH0_BOOT		0xffff
#define CONFIG_SYS_LATCH1_RESET		0xffbf
#define CONFIG_SYS_LATCH1_BOOT		0xffff

#endif	/* __CONFIG_H */
Commit	Line	Data
a605ea7e DE	1	/*
	2	* (C) Copyright 2010
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#define CONFIG_405EP 1 /* this is a PPC405 CPU */
a605ea7e DE	12	#define CONFIG_IO 1 /* on a Io board */
	13
	14	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	15
	16	/*
	17	* Include common defines/options for all AMCC eval boards
	18	*/
	19	#define CONFIG_HOSTNAME io
a605ea7e DE	20	#include "amcc-common.h"
a605ea7e DE	21
6e9e6c36	22	#define CONFIG_BOARD_EARLY_INIT_R
b19bf834	23	#define CONFIG_MISC_INIT_R
6e9e6c36	24	#define CONFIG_LAST_STAGE_INIT
a605ea7e DE	25
	26	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	27
	28	/*
	29	* Configure PLL
	30	*/
	31	#define PLLMR0_DEFAULT PLLMR0_266_133_66
	32	#define PLLMR1_DEFAULT PLLMR1_266_133_66
	33
	34	/* new uImage format support */
9a4f479b	35	#define CONFIG_FIT_DISABLE_SHA256
a605ea7e DE	36
	37	#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
	38
	39	/*
	40	* Default environment variables
	41	*/
	42	#define CONFIG_EXTRA_ENV_SETTINGS \
	43	CONFIG_AMCC_DEF_ENV \
	44	CONFIG_AMCC_DEF_ENV_POWERPC \
	45	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	46	"kernel_addr=fc000000\0" \
	47	"fdt_addr=fc1e0000\0" \
	48	"ramdisk_addr=fc200000\0" \
	49	""
	50
	51	#define CONFIG_PHY_ADDR 4 /* PHY address */
	52	#define CONFIG_HAS_ETH0
	53	#define CONFIG_HAS_ETH1
	54	#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
	55	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
	56
	57	/*
	58	* Commands additional to the ones defined in amcc-common.h
	59	*/
b19bf834	60	#define CONFIG_CMD_DTT
4fb9b41b	61	#undef CONFIG_CMD_DIAG
a605ea7e	62	#undef CONFIG_CMD_EEPROM
4fb9b41b	63	#undef CONFIG_CMD_IRQ
a605ea7e DE	64
	65	/*
	66	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	67	*/
	68	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	69
	70	/* SDRAM timings used in datasheet */
	71	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	72	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	73	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
	74	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	75	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
	76
	77	/*
	78	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	79	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	80	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
	81	* The Linux BASE_BAUD define should match this configuration.
	82	* baseBaud = cpuClock/(uartDivisor*16)
	83	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
	84	* set Linux BASE_BAUD to 403200.
	85	*/
	86	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	87	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	88	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	89	#define CONFIG_SYS_BASE_BAUD 691200
	90
	91	/*
	92	* I2C stuff
	93	*/
880540de	94	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
a605ea7e DE	95
	96	/* Temp sensor/hwmon/dtt */
	97	#define CONFIG_DTT_LM63 1 /* National LM63 */
	98	#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
	99	#define CONFIG_DTT_PWM_LOOKUPTABLE \
	100	{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
	101	#define CONFIG_DTT_TACH_LIMIT 0xa10
	102
	103	/*
	104	* FLASH organization
	105	*/
	106	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	107	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	108
	109	#define CONFIG_SYS_FLASH_BASE 0xFC000000
	110	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	111
	112	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	113	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
	114
	115	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
	116	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
	117
	118	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
a605ea7e DE	119
	120	#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
	121	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
	122
	123	#ifdef CONFIG_ENV_IS_IN_FLASH
	124	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	125	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
	126	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	127
	128	/* Address and size of Redundant Environment Sector */
	129	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
	130	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	131	#endif
	132
	133	/* Gbit PHYs */
	134	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	135	#define CONFIG_BITBANGMII_MULTI
	136
	137	#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
	138	#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
	139
	140	#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
	141
	142	/*
	143	* PPC405 GPIO Configuration
	144	*/
	145	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
	146	{ \
	147	/* GPIO Core 0 */ \
	148	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
	149	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	150	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	151	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	152	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	153	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
	154	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
	155	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
	156	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	157	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
	158	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	159	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	160	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	161	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	162	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
	163	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
	164	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
	165	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
	166	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
	167	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
	168	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
	169	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
	170	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
	171	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
	172	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
	173	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	174	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	175	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
	176	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
	177	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	178	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
	179	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
	180	} \
	181	}
	182
183	/*
184	* Definitions for initial stack pointer and data area (in data cache)
185	*/
186	/* use on chip memory (OCM) for temperary stack until sdram is tested */
187	#define CONFIG_SYS_TEMP_STACK_OCM 1
188
189	/* On Chip Memory location */
190	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
191	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
192	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
b39d1213	193	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
a605ea7e	194
a605ea7e	195	#define CONFIG_SYS_GBL_DATA_OFFSET \
b39d1213	196	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
a605ea7e DE	197	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	198
	199	/*
	200	* External Bus Controller (EBC) Setup
	201	*/
	202
	203	/* Memory Bank 0 (NOR-FLASH) initialization */
	204	#define CONFIG_SYS_EBC_PB0AP 0xa382a880
	205	/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
	206	#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
	207
	208	/* Memory Bank 1 (NVRAM) initializatio */
	209	#define CONFIG_SYS_EBC_PB1AP 0x92015480
	210	/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
	211	#define CONFIG_SYS_EBC_PB1CR 0x7f318000
	212
	213	/* Memory Bank 2 (FPGA) initialization */
2da0fc0d	214	#define CONFIG_SYS_FPGA0_BASE 0x7f100000
a605ea7e DE	215	#define CONFIG_SYS_EBC_PB2AP 0x02025080
	216	/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
	217	#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
	218
2da0fc0d DE	219	#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
	220	#define CONFIG_SYS_FPGA_DONE(k) 0x0010
	221
	222	#define CONFIG_SYS_FPGA_COUNT 1
a605ea7e	223
aba27acf DE	224	#define CONFIG_SYS_FPGA_PTR \
	225	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
	226
	227	#define CONFIG_SYS_FPGA_COMMON
	228
a605ea7e DE	229	/* Memory Bank 3 (Latches) initialization */
	230	#define CONFIG_SYS_LATCH_BASE 0x7f200000
	231	#define CONFIG_SYS_EBC_PB3AP 0xa2015480
	232	/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
	233	#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
	234
	235	#define CONFIG_SYS_LATCH0_RESET 0xffff
	236	#define CONFIG_SYS_LATCH0_BOOT 0xffff
	237	#define CONFIG_SYS_LATCH1_RESET 0xffbf
	238	#define CONFIG_SYS_LATCH1_BOOT 0xffff
	239
	240	#endif /* __CONFIG_H */