projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 255ef4d9 DE |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
| 4 | * | |
| 5 | * based on kilauea.h | |
| 6 | * by Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 7 | * and Grant Erickson <gerickson@nuovations.com> | |
| 8 | * | |
| 3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 255ef4d9 DE |
10 | */ |
| 11 | ||
| 12 | /************************************************************************ | |
| 13 | * io64.h - configuration for Guntermann & Drunck Io64 (405EX) | |
| 14 | ***********************************************************************/ | |
| 15 | ||
| 16 | #ifndef __CONFIG_H | |
| 17 | #define __CONFIG_H | |
| 18 | ||
| 19 | /*----------------------------------------------------------------------- | |
| 20 | * High Level Configuration Options | |
| 21 | *----------------------------------------------------------------------*/ | |
| 22 | #define CONFIG_IO64 1 /* Board is Io64 */ | |
| 255ef4d9 DE |
23 | #define CONFIG_405EX 1 /* Specifc 405EX support*/ |
| 24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ | |
| 25 | ||
| 26 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 27 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
| 28 | #endif | |
| 29 | ||
| 30 | /* | |
| 31 | * CHIP_21 errata | |
| 32 | */ | |
| 33 | #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY | |
| 34 | ||
| 35 | /* | |
| 36 | * Include common defines/options for all AMCC eval boards | |
| 37 | */ | |
| 38 | #define CONFIG_HOSTNAME io64 | |
| 255ef4d9 DE |
39 | #include "amcc-common.h" |
| 40 | ||
| 41 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 42 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 43 | #define CONFIG_MISC_INIT_R | |
| 44 | #define CONFIG_LAST_STAGE_INIT | |
| 45 | ||
| 255ef4d9 DE |
46 | /*----------------------------------------------------------------------- |
| 47 | * Base addresses -- Note these are effective addresses where the | |
| 48 | * actual resources get mapped (not physical addresses) | |
| 49 | *----------------------------------------------------------------------*/ | |
| 50 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
| 51 | #define CONFIG_SYS_NVRAM_BASE 0xF0000000 | |
| 52 | #define CONFIG_SYS_FPGA0_BASE 0xF0100000 | |
| 53 | #define CONFIG_SYS_FPGA1_BASE 0xF0108000 | |
| 54 | #define CONFIG_SYS_LATCH_BASE 0xF0200000 | |
| 55 | ||
| 56 | /*----------------------------------------------------------------------- | |
| 57 | * Initial RAM & Stack Pointer Configuration Options | |
| 58 | * | |
| 59 | * There are traditionally three options for the primordial | |
| 60 | * (i.e. initial) stack usage on the 405-series: | |
| 61 | * | |
| 62 | * 1) On-chip Memory (OCM) (i.e. SRAM) | |
| 63 | * 2) Data cache | |
| 64 | * 3) SDRAM | |
| 65 | * | |
| 66 | * For the 405EX(r), there is no OCM, so we are left with (2) or (3) | |
| 67 | * the latter of which is less than desireable since it requires | |
| 68 | * setting up the SDRAM and ECC in assembly code. | |
| 69 | * | |
| 70 | * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip | |
| 71 | * select on the External Bus Controller (EBC) and then select a | |
| 72 | * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, | |
| 73 | * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and | |
| 74 | * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, | |
| 75 | * physical SDRAM to use (3). | |
| 76 | *-----------------------------------------------------------------------*/ | |
| 77 | ||
| 78 | #define CONFIG_SYS_INIT_DCACHE_CS 4 | |
| 79 | ||
| 80 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) | |
| 81 | #define CONFIG_SYS_INIT_RAM_ADDR \ | |
| 82 | (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */ | |
| 83 | #else | |
| 84 | #define CONFIG_SYS_INIT_RAM_ADDR \ | |
| 85 | (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ | |
| 86 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
| 87 | ||
| 88 | #define CONFIG_SYS_INIT_RAM_SIZE \ | |
| 89 | (4 << 10) /* 4 KiB */ | |
| 90 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
| 91 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 92 | ||
| 93 | /* | |
| 94 | * If the data cache is being used for the primordial stack and global | |
| 95 | * data area, the POST word must be placed somewhere else. The General | |
| 96 | * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves | |
| 97 | * its compare and mask register contents across reset, so it is used | |
| 98 | * for the POST word. | |
| 99 | */ | |
| 100 | ||
| 101 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) | |
| 102 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 103 | # define CONFIG_SYS_POST_WORD_ADDR \ | |
| 104 | (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) | |
| 105 | #else | |
| 106 | # define CONFIG_SYS_INIT_EXTRA_SIZE 16 | |
| 107 | # define CONFIG_SYS_INIT_SP_OFFSET \ | |
| 108 | (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) | |
| 109 | # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR | |
| 110 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
| 111 | ||
| 112 | /*----------------------------------------------------------------------- | |
| 113 | * Serial Port | |
| 114 | *----------------------------------------------------------------------*/ | |
| 115 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
| 116 | #define CONFIG_SYS_BASE_BAUD 691200 | |
| 117 | ||
| 118 | /*----------------------------------------------------------------------- | |
| 119 | * Environment | |
| 120 | *----------------------------------------------------------------------*/ | |
| 121 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
| 122 | ||
| 123 | /*----------------------------------------------------------------------- | |
| 124 | * FLASH related | |
| 125 | *----------------------------------------------------------------------*/ | |
| 126 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
| 127 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
| 128 | ||
| 129 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
| 130 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 131 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
| 132 | ||
| 133 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
| 134 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
| 135 | ||
| 136 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 137 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 138 | ||
| 139 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
| 140 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
| 141 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) | |
| 142 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
| 143 | ||
| 144 | /* Address and size of Redundant Environment Sector */ | |
| 145 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
| 146 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 147 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
| 148 | ||
| 149 | /* Gbit PHYs */ | |
| 150 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
| 151 | #define CONFIG_BITBANGMII_MULTI | |
| 152 | ||
| 153 | #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */ | |
| 154 | #define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */ | |
| 155 | ||
| 156 | #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0" | |
| 157 | ||
| 158 | #define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */ | |
| 159 | #define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */ | |
| 160 | ||
| 161 | #define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1" | |
| 162 | ||
| 163 | /*----------------------------------------------------------------------- | |
| 164 | * DDR SDRAM | |
| 165 | *----------------------------------------------------------------------*/ | |
| 166 | #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */ | |
| 167 | ||
| 168 | /* | |
| 169 | * CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
| 170 | * | |
| 171 | * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx | |
| 172 | * SDRAM Controller DDR autocalibration values and takes a lot longer | |
| 173 | * to run than Method_B. | |
| 174 | * (See the Method_A and Method_B algorithm discription in the file: | |
| 175 | * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) | |
| 176 | * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A | |
| 177 | * | |
| 178 | * DDR Autocalibration Method_B is the default. | |
| 179 | */ | |
| 180 | #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
| 181 | #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION | |
| 182 | #undef CONFIG_PPC4xx_DDR_METHOD_A | |
| 183 | ||
| 184 | #define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE) | |
| 185 | ||
| 186 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
| 187 | #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ | |
| 188 | SDRAM_RXBAS_SDSZ_128MB | \ | |
| 189 | SDRAM_RXBAS_SDAM_MODE2 | \ | |
| 190 | SDRAM_RXBAS_SDBE_ENABLE) | |
| 191 | #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE | |
| 192 | #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE | |
| 193 | #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE | |
| 194 | #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ | |
| 195 | SDRAM_MCOPT1_4_BANKS | \ | |
| 196 | SDRAM_MCOPT1_DDR2_TYPE | \ | |
| 197 | SDRAM_MCOPT1_QDEP | \ | |
| 198 | SDRAM_MCOPT1_DCOO_DISABLED) | |
| 199 | #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 | |
| 200 | #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ | |
| 201 | SDRAM_MODT_EB0R_ENABLE) | |
| 202 | #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 | |
| 203 | #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ | |
| 204 | SDRAM_CODT_CKLZ_36OHM | \ | |
| 205 | SDRAM_CODT_DQS_1_8_V_DDR2 | \ | |
| 206 | SDRAM_CODT_IO_NMODE) | |
| 207 | #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) | |
| 208 | #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ | |
| 209 | SDRAM_INITPLR_IMWT_ENCODE(80) | \ | |
| 210 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) | |
| 211 | #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ | |
| 212 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ | |
| 213 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
| 214 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 215 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
| 216 | #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ | |
| 217 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 218 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 219 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ | |
| 220 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) | |
| 221 | #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ | |
| 222 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 223 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 224 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ | |
| 225 | SDRAM_INITPLR_IMA_ENCODE(0)) | |
| 226 | #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ | |
| 227 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 228 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 229 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 230 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 231 | JEDEC_MA_EMR_RTT_75OHM)) | |
| 232 | #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ | |
| 233 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 234 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 235 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 236 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
| 237 | JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ | |
| 238 | JEDEC_MA_MR_BLEN_4 | \ | |
| 239 | JEDEC_MA_MR_DLL_RESET)) | |
| 240 | #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ | |
| 241 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ | |
| 242 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
| 243 | SDRAM_INITPLR_IBA_ENCODE(0x0) | \ | |
| 244 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
| 245 | #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ | |
| 246 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
| 247 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 248 | #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ | |
| 249 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
| 250 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 251 | #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ | |
| 252 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
| 253 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 254 | #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ | |
| 255 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ | |
| 256 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 257 | #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ | |
| 258 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 259 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 260 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 261 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
| 262 | JEDEC_MA_MR_CL_DDR2_5_0_CLK | \ | |
| 263 | JEDEC_MA_MR_BLEN_4)) | |
| 264 | #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ | |
| 265 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 266 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 267 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 268 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ | |
| 269 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
| 270 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 271 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
| 272 | JEDEC_MA_EMR_ODS_NORMAL)) | |
| 273 | #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ | |
| 274 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ | |
| 275 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 276 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 277 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ | |
| 278 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
| 279 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 280 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
| 281 | JEDEC_MA_EMR_ODS_NORMAL)) | |
| 282 | #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) | |
| 283 | #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) | |
| 284 | #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ | |
| 285 | SDRAM_RQDC_RQFD_ENCODE(56)) | |
| 286 | #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) | |
| 287 | #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) | |
| 288 | #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ | |
| 289 | SDRAM_DLCR_DLCS_CONT_DONE | \ | |
| 290 | SDRAM_DLCR_DLCV_ENCODE(165)) | |
| 291 | #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) | |
| 292 | #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 | |
| 293 | #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ | |
| 294 | SDRAM_SDTR1_RTW_2_CLK | \ | |
| 295 | SDRAM_SDTR1_WTWO_1_CLK | \ | |
| 296 | SDRAM_SDTR1_RTRO_1_CLK) | |
| 297 | #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ | |
| 298 | SDRAM_SDTR2_WTR_2_CLK | \ | |
| 299 | SDRAM_SDTR2_XSNR_32_CLK | \ | |
| 300 | SDRAM_SDTR2_WPC_4_CLK | \ | |
| 301 | SDRAM_SDTR2_RPC_2_CLK | \ | |
| 302 | SDRAM_SDTR2_RP_3_CLK | \ | |
| 303 | SDRAM_SDTR2_RRD_2_CLK) | |
| 304 | #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \ | |
| 305 | SDRAM_SDTR3_RC_ENCODE(12) | \ | |
| 306 | SDRAM_SDTR3_XCS | \ | |
| 307 | SDRAM_SDTR3_RFC_ENCODE(21)) | |
| 308 | #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ | |
| 309 | SDRAM_MMODE_DCL_DDR2_5_0_CLK | \ | |
| 310 | SDRAM_MMODE_BLEN_4) | |
| 311 | #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ | |
| 312 | SDRAM_MEMODE_RTT_75OHM) | |
| 313 | ||
| 314 | /*----------------------------------------------------------------------- | |
| 315 | * I2C | |
| 316 | *----------------------------------------------------------------------*/ | |
| 880540de | 317 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 255ef4d9 DE |
318 | |
| 319 | #define CONFIG_PCA9698 1 /* NXP PCA9698 */ | |
| 320 | ||
| 321 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ | |
| 322 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
| 323 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 324 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 325 | ||
| 326 | /* I2C bootstrap EEPROM */ | |
| 327 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 | |
| 328 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
| 329 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
| 330 | ||
| 331 | /* Temp sensor/hwmon/dtt */ | |
| 332 | #define CONFIG_DTT_LM63 1 /* National LM63 */ | |
| 333 | #define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ | |
| 334 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ | |
| 335 | { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ | |
| 336 | { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } | |
| 337 | #define CONFIG_DTT_TACH_LIMIT 0xa10 | |
| 338 | ||
| 339 | /*----------------------------------------------------------------------- | |
| 340 | * Ethernet | |
| 341 | *----------------------------------------------------------------------*/ | |
| 342 | #define CONFIG_M88E1111_PHY 1 | |
| 343 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 344 | #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII | |
| 345 | #define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */ | |
| 346 | ||
| 347 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 348 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 349 | ||
| 350 | #define CONFIG_HAS_ETH0 1 | |
| 351 | ||
| 352 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
| 353 | #define CONFIG_PHY1_ADDR 0x13 | |
| 354 | ||
| 355 | /* Debug messages for the DDR autocalibration */ | |
| 356 | #define CONFIG_AUTOCALIB "silent\0" | |
| 357 | ||
| 358 | /* | |
| 359 | * Default environment variables | |
| 360 | */ | |
| 361 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 362 | CONFIG_AMCC_DEF_ENV \ | |
| 363 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 364 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
| 365 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 366 | "logversion=2\0" \ | |
| 367 | "kernel_addr=fc000000\0" \ | |
| 368 | "fdt_addr=fc1e0000\0" \ | |
| 369 | "ramdisk_addr=fc200000\0" \ | |
| 370 | "pciconfighost=1\0" \ | |
| 371 | "pcie_mode=RP:RP\0" \ | |
| 372 | "" | |
| 373 | ||
| 374 | /* | |
| 375 | * Commands additional to the ones defined in amcc-common.h | |
| 376 | */ | |
| 377 | #define CONFIG_CMD_CHIP_CONFIG | |
| 378 | #define CONFIG_CMD_DTT | |
| 379 | ||
| 380 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
| 381 | ||
| 382 | /* POST support */ | |
| 383 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ | |
| 384 | CONFIG_SYS_POST_CPU | \ | |
| 385 | CONFIG_SYS_POST_ETHER | \ | |
| 386 | CONFIG_SYS_POST_I2C | \ | |
| 387 | CONFIG_SYS_POST_MEMORY_ON | \ | |
| 388 | CONFIG_SYS_POST_UART) | |
| 389 | ||
| 390 | /* Define here the base-addresses of the UARTs to test in POST */ | |
| 391 | #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ | |
| 392 | CONFIG_SYS_NS16550_COM2 } | |
| 393 | ||
| 394 | #define CONFIG_LOGBUFFER | |
| 395 | #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ | |
| 396 | ||
| 397 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 398 | ||
| 399 | /*----------------------------------------------------------------------- | |
| 400 | * External Bus Controller (EBC) Setup | |
| 401 | *----------------------------------------------------------------------*/ | |
| 402 | ||
| 403 | /* Memory Bank 0 (NOR-flash) */ | |
| 404 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
| 405 | EBC_BXAP_TWT_ENCODE(11) | \ | |
| 406 | EBC_BXAP_BCE_DISABLE | \ | |
| 407 | EBC_BXAP_BCT_2TRANS | \ | |
| 408 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 409 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 410 | EBC_BXAP_WBN_ENCODE(1) | \ | |
| 411 | EBC_BXAP_WBF_ENCODE(2) | \ | |
| 412 | EBC_BXAP_TH_ENCODE(2) | \ | |
| 413 | EBC_BXAP_RE_DISABLED | \ | |
| 414 | EBC_BXAP_SOR_NONDELAYED | \ | |
| 415 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 416 | EBC_BXAP_PEN_DISABLED) | |
| 417 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ | |
| 418 | EBC_BXCR_BS_64MB | \ | |
| 419 | EBC_BXCR_BU_RW | \ | |
| 420 | EBC_BXCR_BW_16BIT) | |
| 421 | ||
| 422 | /* Memory Bank 1 (NVRAM/Uart) */ | |
| 423 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \ | |
| 424 | EBC_BXAP_FWT_ENCODE(8) | \ | |
| 425 | EBC_BXAP_BWT_ENCODE(4) | \ | |
| 426 | EBC_BXAP_BCE_DISABLE | \ | |
| 427 | EBC_BXAP_BCT_2TRANS | \ | |
| 428 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 429 | EBC_BXAP_OEN_ENCODE(1) | \ | |
| 430 | EBC_BXAP_WBN_ENCODE(1) | \ | |
| 431 | EBC_BXAP_WBF_ENCODE(1) | \ | |
| 432 | EBC_BXAP_TH_ENCODE(2) | \ | |
| 433 | EBC_BXAP_RE_DISABLED | \ | |
| 434 | EBC_BXAP_SOR_NONDELAYED | \ | |
| 435 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 436 | EBC_BXAP_PEN_DISABLED) | |
| 437 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \ | |
| 438 | EBC_BXCR_BS_1MB | \ | |
| 439 | EBC_BXCR_BU_RW | \ | |
| 440 | EBC_BXCR_BW_8BIT) | |
| 441 | ||
| 442 | /* Memory Bank 2 (FPGA) */ | |
| 443 | #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ | |
| 444 | EBC_BXAP_TWT_ENCODE(5) | \ | |
| 445 | EBC_BXAP_BCE_DISABLE | \ | |
| 446 | EBC_BXAP_BCT_2TRANS | \ | |
| 447 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 448 | EBC_BXAP_OEN_ENCODE(2) | \ | |
| 449 | EBC_BXAP_WBN_ENCODE(1) | \ | |
| 450 | EBC_BXAP_WBF_ENCODE(1) | \ | |
| 451 | EBC_BXAP_TH_ENCODE(0) | \ | |
| 452 | EBC_BXAP_RE_DISABLED | \ | |
| 453 | EBC_BXAP_SOR_NONDELAYED | \ | |
| 454 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 455 | EBC_BXAP_PEN_DISABLED) | |
| 456 | #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ | |
| 457 | EBC_BXCR_BS_1MB | \ | |
| 458 | EBC_BXCR_BU_RW | \ | |
| 459 | EBC_BXCR_BW_16BIT) | |
| 460 | ||
| 461 | /* Memory Bank 3 (Latches) */ | |
| 462 | #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ | |
| 463 | EBC_BXAP_FWT_ENCODE(8) | \ | |
| 464 | EBC_BXAP_BWT_ENCODE(4) | \ | |
| 465 | EBC_BXAP_BCE_DISABLE | \ | |
| 466 | EBC_BXAP_BCT_2TRANS | \ | |
| 467 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 468 | EBC_BXAP_OEN_ENCODE(1) | \ | |
| 469 | EBC_BXAP_WBN_ENCODE(1) | \ | |
| 470 | EBC_BXAP_WBF_ENCODE(1) | \ | |
| 471 | EBC_BXAP_TH_ENCODE(2) | \ | |
| 472 | EBC_BXAP_RE_DISABLED | \ | |
| 473 | EBC_BXAP_SOR_NONDELAYED | \ | |
| 474 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 475 | EBC_BXAP_PEN_DISABLED) | |
| 476 | #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ | |
| 477 | EBC_BXCR_BS_1MB | \ | |
| 478 | EBC_BXCR_BU_RW | \ | |
| 479 | EBC_BXCR_BW_16BIT) | |
| 480 | ||
| 481 | /* EBC peripherals */ | |
| 482 | ||
| 483 | #define CONFIG_SYS_FPGA_BASE(k) \ | |
| 484 | (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) | |
| 485 | ||
| 486 | #define CONFIG_SYS_FPGA_DONE(k) \ | |
| 487 | (k ? 0x0040 : 0x0080) | |
| 488 | ||
| 489 | #define CONFIG_SYS_FPGA_COUNT 2 | |
| 490 | ||
| aba27acf DE |
491 | #define CONFIG_SYS_FPGA_PTR { \ |
| 492 | (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ | |
| 493 | (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } | |
| 494 | ||
| 495 | #define CONFIG_SYS_FPGA_COMMON | |
| 496 | ||
| 255ef4d9 DE |
497 | #define CONFIG_SYS_LATCH0_RESET 0xffff |
| 498 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
| 499 | #define CONFIG_SYS_LATCH1_RESET 0xffbf | |
| 500 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
| 501 | ||
| 502 | /*----------------------------------------------------------------------- | |
| 503 | * GPIO Setup | |
| 504 | *----------------------------------------------------------------------*/ | |
| 505 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \ | |
| 506 | { \ | |
| 507 | /* GPIO Core 0 */ \ | |
| 508 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \ | |
| 509 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \ | |
| 510 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \ | |
| 511 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \ | |
| 512 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \ | |
| 513 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \ | |
| 514 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \ | |
| 515 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \ | |
| 516 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \ | |
| 517 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \ | |
| 518 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \ | |
| 519 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \ | |
| 520 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \ | |
| 521 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \ | |
| 522 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \ | |
| 523 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \ | |
| 524 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \ | |
| 525 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \ | |
| 526 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \ | |
| 527 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \ | |
| 528 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \ | |
| 529 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \ | |
| 530 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \ | |
| 531 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \ | |
| 532 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \ | |
| 533 | {GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \ | |
| 534 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \ | |
| 535 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \ | |
| 536 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \ | |
| 537 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \ | |
| 538 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \ | |
| 539 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \ | |
| 540 | } \ | |
| 541 | } | |
| 542 | ||
| 543 | #define CONFIG_SYS_GPIO_STARTUP_FINISHED 15 | |
| 544 | #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14 | |
| 545 | ||
| 546 | #endif /* __CONFIG_H */ |