[people/ms/u-boot.git] / include / configs / iocon.h

/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_405EP		1	/* this is a PPC405 CPU */
#define CONFIG_IOCON		1	/*  on a IoCon board */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		iocon
#define CONFIG_IDENT_STRING	" iocon 0.06"
#include "amcc-common.h"

/* Reclaim some space. */
#undef CONFIG_SYS_LONGHELP

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT

#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */

/*
 * Configure PLL
 */
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66

#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */

/* new uImage format support */
#define CONFIG_FIT_DISABLE_SHA256

#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	""

#define CONFIG_PHY_ADDR		4	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_FPGAD
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IRQ

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */

/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#define CONFIG_CONS_INDEX		1	/* Use UART0 */
#undef  CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
#undef  CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		691200

/*
 * I2C stuff
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_IHS

#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_SPD_BUS_NUM		4

#define CONFIG_PCA953X			/* NXP PCA9554 */
#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2
#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
#define CONFIG_SYS_I2C_IHS_CH3
#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
#define I2C_SOFT_DECLARATIONS3
#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F

#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
#define CONFIG_SYS_DP501_I2C			{0, 1, 2, 3}

#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
#endif

#define I2C_ACTIVE	{ }
#define I2C_TRISTATE	{ }
#define I2C_READ \
	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
#define I2C_SDA(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
		else \
			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
	} while (0)
#define I2C_SCL(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
		else \
			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
	} while (0)
#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */

#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*
 * PPC405 GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
} \
}

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP		0xa382a880
#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000

/* Memory Bank 1 (NVRAM) initializatio */
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xFB858000

/* Memory Bank 2 (FPGA0) initialization */
#define CONFIG_SYS_FPGA0_BASE		0x7f100000
#define CONFIG_SYS_EBC_PB2AP		0x02825080
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)

#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k)		0x0010

#define CONFIG_SYS_FPGA_COUNT		1

#define CONFIG_SYS_MCLINK_MAX		3

#define CONFIG_SYS_FPGA_PTR \
	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }

/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE		0x7f200000
#define CONFIG_SYS_EBC_PB3AP		0x02025080
#define CONFIG_SYS_EBC_PB3CR		0x7f21a000

#define CONFIG_SYS_LATCH0_RESET		0xffef
#define CONFIG_SYS_LATCH0_BOOT		0xffff
#define CONFIG_SYS_LATCH1_RESET		0xffff
#define CONFIG_SYS_LATCH1_BOOT		0xffff

/*
 * OSD Setup
 */
#define CONFIG_SYS_MPC92469AC
#define CONFIG_SYS_OSD_SCREENS		1
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */

#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI

#endif	/* __CONFIG_H */
Commit	Line	Data
a605ea7e DE	1	/*
	2	* (C) Copyright 2010
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#define CONFIG_405EP 1 /* this is a PPC405 CPU */
a605ea7e DE	12	#define CONFIG_IOCON 1 /* on a IoCon board */
	13
	14	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	15
	16	/*
	17	* Include common defines/options for all AMCC eval boards
	18	*/
	19	#define CONFIG_HOSTNAME iocon
cccd4f40	20	#define CONFIG_IDENT_STRING " iocon 0.06"
a605ea7e DE	21	#include "amcc-common.h"
a605ea7e DE	22
57e5ecaf TR	23	/* Reclaim some space. */
	24	#undef CONFIG_SYS_LONGHELP
	25
6e9e6c36 DE	26	#define CONFIG_BOARD_EARLY_INIT_F
6e9e6c36 DE	27	#define CONFIG_BOARD_EARLY_INIT_R
a605ea7e DE	28	#define CONFIG_LAST_STAGE_INIT
	29
	30	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	31
	32	/*
	33	* Configure PLL
	34	*/
	35	#define PLLMR0_DEFAULT PLLMR0_266_133_66
	36	#define PLLMR1_DEFAULT PLLMR1_266_133_66
	37
996d88d8	38	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
996d88d8	39
a605ea7e	40	/* new uImage format support */
9a4f479b	41	#define CONFIG_FIT_DISABLE_SHA256
a605ea7e DE	42
	43	#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
	44
	45	/*
	46	* Default environment variables
	47	*/
	48	#define CONFIG_EXTRA_ENV_SETTINGS \
	49	CONFIG_AMCC_DEF_ENV \
	50	CONFIG_AMCC_DEF_ENV_POWERPC \
	51	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	52	"kernel_addr=fc000000\0" \
	53	"fdt_addr=fc1e0000\0" \
	54	"ramdisk_addr=fc200000\0" \
	55	""
	56
	57	#define CONFIG_PHY_ADDR 4 /* PHY address */
	58	#define CONFIG_HAS_ETH0
	59	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
	60
	61	/*
	62	* Commands additional to the ones defined in amcc-common.h
	63	*/
7d2357c1	64	#define CONFIG_CMD_FPGAD
a605ea7e	65	#undef CONFIG_CMD_EEPROM
4fb9b41b	66	#undef CONFIG_CMD_IRQ
a605ea7e DE	67
	68	/*
	69	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	70	*/
	71	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	72
	73	/* SDRAM timings used in datasheet */
	74	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	75	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	76	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
	77	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	78	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
	79
	80	/*
	81	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	82	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	83	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
	84	* The Linux BASE_BAUD define should match this configuration.
	85	* baseBaud = cpuClock/(uartDivisor*16)
	86	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
	87	* set Linux BASE_BAUD to 403200.
	88	*/
	89	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	90	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	91	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	92	#define CONFIG_SYS_BASE_BAUD 691200
	93
	94	/*
	95	* I2C stuff
	96	*/
ea818dbb	97	#define CONFIG_SYS_I2C
880540de DE	98	#define CONFIG_SYS_I2C_PPC4XX
	99	#define CONFIG_SYS_I2C_PPC4XX_CH0
	100	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	101	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
b46226bd	102	#define CONFIG_SYS_I2C_IHS
a605ea7e	103
e50e8968	104	#define CONFIG_SYS_I2C_SPEED 400000
b46226bd	105	#define CONFIG_SYS_SPD_BUS_NUM 4
e50e8968 DE	106
	107	#define CONFIG_PCA953X /* NXP PCA9554 */
	108	#define CONFIG_PCA9698 /* NXP PCA9698 */
	109
b46226bd DE	110	#define CONFIG_SYS_I2C_IHS_CH0
	111	#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
	112	#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
	113	#define CONFIG_SYS_I2C_IHS_CH1
	114	#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
	115	#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
	116	#define CONFIG_SYS_I2C_IHS_CH2
	117	#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
	118	#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
	119	#define CONFIG_SYS_I2C_IHS_CH3
	120	#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
	121	#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
	122
a605ea7e DE	123	/*
	124	* Software (bit-bang) I2C driver configuration
	125	*/
e50e8968 DE	126	#define CONFIG_SYS_I2C_SOFT
	127	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	128	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
	129	#define I2C_SOFT_DECLARATIONS2
	130	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
	131	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
	132	#define I2C_SOFT_DECLARATIONS3
	133	#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
	134	#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
	135	#define I2C_SOFT_DECLARATIONS4
	136	#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
	137	#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
	138
b46226bd DE	139	#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
	140	#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
	141	#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
a605ea7e DE	142
a605ea7e DE	143	#ifndef __ASSEMBLY__
e50e8968 DE	144	void fpga_gpio_set(unsigned int bus, int pin);
	145	void fpga_gpio_clear(unsigned int bus, int pin);
	146	int fpga_gpio_get(unsigned int bus, int pin);
a605ea7e DE	147	#endif
	148
	149	#define I2C_ACTIVE { }
	150	#define I2C_TRISTATE { }
e50e8968 DE	151	#define I2C_READ \
	152	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
	153	#define I2C_SDA(bit) \
	154	do { \
	155	if (bit) \
	156	fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
	157	else \
	158	fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
	159	} while (0)
	160	#define I2C_SCL(bit) \
	161	do { \
	162	if (bit) \
	163	fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
	164	else \
	165	fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
	166	} while (0)
a605ea7e DE	167	#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
	168
	169	/*
	170	* FLASH organization
	171	*/
	172	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	173	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	174
	175	#define CONFIG_SYS_FLASH_BASE 0xFC000000
	176	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	177
	178	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	179	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
	180
	181	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
	182	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
	183
	184	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
a605ea7e DE	185
	186	#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
	187	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
	188
	189	#ifdef CONFIG_ENV_IS_IN_FLASH
	190	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	191	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
	192	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	193
	194	/* Address and size of Redundant Environment Sector */
	195	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
	196	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	197	#endif
	198
	199	/*
	200	* PPC405 GPIO Configuration
	201	*/
	202	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
	203	{ \
	204	/* GPIO Core 0 */ \
	205	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
	206	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	207	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	208	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	209	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	210	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
	211	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
	212	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
	213	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	214	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
	215	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	216	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	217	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	218	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	219	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
	220	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
	221	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
	222	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
	223	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
	224	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
	225	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
	226	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
	227	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
	228	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
	229	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
	230	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	231	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	232	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
	233	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
	234	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	235	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
	236	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
	237	} \
	238	}
	239
	240	/*
	241	* Definitions for initial stack pointer and data area (in data cache)
	242	*/
	243	/* use on chip memory (OCM) for temperary stack until sdram is tested */
	244	#define CONFIG_SYS_TEMP_STACK_OCM 1
	245
	246	/* On Chip Memory location */
	247	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	248	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
249	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
b39d1213	250	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
a605ea7e	251
a605ea7e	252	#define CONFIG_SYS_GBL_DATA_OFFSET \
b39d1213	253	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
a605ea7e DE	254	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	255
	256	/*
	257	* External Bus Controller (EBC) Setup
	258	*/
	259
	260	/* Memory Bank 0 (NOR-FLASH) initialization */
	261	#define CONFIG_SYS_EBC_PB0AP 0xa382a880
	262	#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
	263
	264	/* Memory Bank 1 (NVRAM) initializatio */
	265	#define CONFIG_SYS_EBC_PB1AP 0x92015480
	266	#define CONFIG_SYS_EBC_PB1CR 0xFB858000
	267
2da0fc0d DE	268	/* Memory Bank 2 (FPGA0) initialization */
2da0fc0d DE	269	#define CONFIG_SYS_FPGA0_BASE 0x7f100000
a605ea7e	270	#define CONFIG_SYS_EBC_PB2AP 0x02825080
2da0fc0d DE	271	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE \| 0x1a000)
	272
	273	#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
	274	#define CONFIG_SYS_FPGA_DONE(k) 0x0010
a605ea7e	275
2da0fc0d	276	#define CONFIG_SYS_FPGA_COUNT 1
a605ea7e	277
e50e8968	278	#define CONFIG_SYS_MCLINK_MAX 3
aba27acf	279
e50e8968 DE	280	#define CONFIG_SYS_FPGA_PTR \
e50e8968 DE	281	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
aba27acf	282
a605ea7e DE	283	/* Memory Bank 3 (Latches) initialization */
	284	#define CONFIG_SYS_LATCH_BASE 0x7f200000
	285	#define CONFIG_SYS_EBC_PB3AP 0x02025080
	286	#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
	287
	288	#define CONFIG_SYS_LATCH0_RESET 0xffef
	289	#define CONFIG_SYS_LATCH0_BOOT 0xffff
	290	#define CONFIG_SYS_LATCH1_RESET 0xffff
	291	#define CONFIG_SYS_LATCH1_BOOT 0xffff
	292
2da0fc0d DE	293	/*
	294	* OSD Setup
	295	*/
	296	#define CONFIG_SYS_MPC92469AC
e50e8968	297	#define CONFIG_SYS_OSD_SCREENS 1
edfe9fea DE	298	#define CONFIG_SYS_DP501_DIFFERENTIAL
edfe9fea DE	299	#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
e50e8968 DE	300
	301	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	302	#define CONFIG_BITBANGMII_MULTI
2da0fc0d	303
a605ea7e	304	#endif /* __CONFIG_H */