[people/ms/u-boot.git] / include / configs / ipek01.h

/*
 * (C) Copyright 2006
 * MicroSys GmbH
 *
 * (C) Copyright 2009
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPX5200		1	/* ... on MPX5200 board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
#define CONFIG_IPEK01           	/* Motherboard is ipek01 */

#define	CONFIG_SYS_TEXT_BASE	0xfc000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */

#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */

/*
 * Video configuration for LIME GDC
 */
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
/* Lime clock frequency */
#define CONFIG_SYS_MB862xx_CCF	0x90000	/* geo 166MHz other 133MHz */
/* SDRAM parameter */
#define CONFIG_SYS_MB862xx_MMR	0x41c767e3
#endif

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */

/* Partitions */
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_USB_STORAGE

#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP		/* BMP support */
#endif
#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP		/* DHCP Support */
#define CONFIG_CMD_FAT		/* FAT support */
#define CONFIG_CMD_I2C		/* I2C serial bus support */
#define CONFIG_CMD_IDE		/* IDE harddisk support */
#define CONFIG_CMD_IRQ		/* irqinfo */
#define CONFIG_CMD_MII		/* MII support */
#define CONFIG_CMD_PCI		/* pciinfo */
#define CONFIG_CMD_USB		/* USB Support */

#define CONFIG_SYS_LOWBOOT	1

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyPSC0\0"						\
	"hostname=ipek01\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consoledev},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
		"run nfsargs addip addtty;"    				\
		 "bootm ${loadaddr} - ${fdtaddr}\0"			\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=ipek01/uImage\0"					\
	"load=tftp 100000 ipek01/u-boot.bin\0"				\
	"update=protect off FC000000 +60000; era FC000000 +60000; "	\
		"cp.b 100000 FC000000 ${filesize}\0"   			\
	"upd=run load;run update\0"					\
	"fdtaddr=800000\0"						\
	"loadaddr=400000\0"						\
	"fdtfile=ipek01/ipek01.dtb\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 	/* for 133MHz */
/* PCI clock must be 33, because board will not boot */
#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for 66MHz */

/*
 * Open firmware flat tree support
 */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE	2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED	100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
					 CONFIG_SYS_MONITOR_LEN)

#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256  /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */

/* use CFI flash driver */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SIZE			0x10000
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_OVERWRITE		1
#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR			0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
#define	CONFIG_SYS_SRAM_BASE		0xF1000000
#define	CONFIG_SYS_SRAM_SIZE		0x00200000
#define	CONFIG_SYS_LIME_BASE		0xE4000000
#define	CONFIG_SYS_LIME_SIZE		0x04000000
#define	CONFIG_SYS_FPGA_BASE		0xC0000000
#define	CONFIG_SYS_FPGA_SIZE		0x10000000
#define	CONFIG_SYS_MPEG_BASE		0xe2000000
#define	CONFIG_SYS_MPEG_SIZE		0x01000000
#define CONFIG_SYS_CF_BASE		0xe1000000
#define CONFIG_SYS_CF_SIZE		0x01000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
/* End of used area in DPRAM */
#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE

/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
					 CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN	(384 << 10)  /* Reserve 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN	(4 << 20)    /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)    /* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC		1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR			0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x1d556624

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS		16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1...15 MB in DRAM */

#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */

#define CONFIG_SYS_HZ			1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
#define CONFIG_SYS_CS3_START		CONFIG_SYS_LIME_BASE
#define CONFIG_SYS_CS3_SIZE		CONFIG_SYS_LIME_SIZE
#define	CONFIG_SYS_CS6_START		CONFIG_SYS_FPGA_BASE
#define	CONFIG_SYS_CS6_SIZE		CONFIG_SYS_FPGA_SIZE
#define	CONFIG_SYS_CS5_START		CONFIG_SYS_CF_BASE
#define	CONFIG_SYS_CS5_SIZE		CONFIG_SYS_CF_SIZE
#define	CONFIG_SYS_CS7_START		CONFIG_SYS_MPEG_BASE
#define	CONFIG_SYS_CS7_SIZE		CONFIG_SYS_MPEG_SIZE

#ifdef CONFIG_SYS_PCISPEED_66
#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
#define CONFIG_SYS_CS1_CFG		0x0004FB00
#define CONFIG_SYS_CS2_CFG		0x0006F900
#else
#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
#define CONFIG_SYS_CS1_CFG		0x0001FB00
#define CONFIG_SYS_CS2_CFG		0x0002F90C
#endif

/*
 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
 * waitstates, writeswap and readswap enabled
 */
#define CONFIG_SYS_CS3_CFG		0x00FFFB0C
#define	CONFIG_SYS_CS6_CFG		0x00FFFB0C
#define	CONFIG_SYS_CS7_CFG		0x4040751C

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE		0x33330000

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK		0x0001BBBB
#define CONFIG_USB_CONFIG		0x00005000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	2 /* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
cd12f615 WG	1	/*
	2	* (C) Copyright 2006
	3	* MicroSys GmbH
	4	*
	5	* (C) Copyright 2009
	6	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	*/
	33
	34	#define CONFIG_MPC5200
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
	37	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	38	#define CONFIG_IPEK01 /* Motherboard is ipek01 */
	39
2ae18241 WD	40	#define CONFIG_SYS_TEXT_BASE 0xfc000000
2ae18241 WD	41
cd12f615 WG	42	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
	43
	44	#define CONFIG_MISC_INIT_R
	45
cd12f615 WG	46	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	47	#ifdef CONFIG_CMD_KGDB
	48	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	49	#endif
	50
	51	/*
	52	* Serial console configuration
	53	*/
	54	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	55	#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
	56	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	57
	58	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	59
	60	/*
	61	* Video configuration for LIME GDC
	62	*/
	63	#define CONFIG_VIDEO
	64	#ifdef CONFIG_VIDEO
	65	#define CONFIG_VIDEO_MB862xx
	66	#define CONFIG_VIDEO_MB862xx_ACCEL
	67	#define VIDEO_FB_16BPP_WORD_SWAP
	68	#define CONFIG_CFB_CONSOLE
	69	#define CONFIG_VIDEO_LOGO
	70	#define CONFIG_VIDEO_BMP_LOGO
	71	#define CONFIG_CONSOLE_EXTRA_INFO
	72	#define CONFIG_VGA_AS_SINGLE_DEVICE
	73	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	74	#define CONFIG_VIDEO_SW_CURSOR
	75	#define CONFIG_SPLASH_SCREEN
	76	#define CONFIG_VIDEO_BMP_GZIP
	77	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
	78	/* Lime clock frequency */
	79	#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
	80	/* SDRAM parameter */
	81	#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
	82	#endif
	83
	84	/*
	85	* PCI Mapping:
	86	* 0x40000000 - 0x4fffffff - PCI Memory
	87	* 0x50000000 - 0x50ffffff - PCI IO Space
	88	*/
	89	#define CONFIG_PCI 1
	90	#define CONFIG_PCI_PNP 1
	91	#define CONFIG_PCI_SCAN_SHOW 1
	92
	93	#define CONFIG_PCI_MEM_BUS 0x40000000
	94	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	95	#define CONFIG_PCI_MEM_SIZE 0x10000000
	96
	97	#define CONFIG_PCI_IO_BUS 0x50000000
	98	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	99	#define CONFIG_PCI_IO_SIZE 0x01000000
	100
	101	#define CONFIG_NET_MULTI 1
	102	#define CONFIG_MII 1
	103	#define CONFIG_EEPRO100 1
	104	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	105
	106	/* Partitions */
	107	#define CONFIG_DOS_PARTITION
	108
	109	/* USB */
110	#define CONFIG_USB_OHCI_NEW
111	#define CONFIG_SYS_OHCI_BE_CONTROLLER
112	#define CONFIG_USB_STORAGE
113
114	#define CONFIG_SYS_USB_OHCI_CPU_INIT
115	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
116	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
117	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
118
119	/*
120	* Command line configuration.
121	*/
122	#include <config_cmd_default.h>
123
124	#ifdef CONFIG_VIDEO
125	#define CONFIG_CMD_BMP /* BMP support */
126	#endif
127	#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
128	#define CONFIG_CMD_DHCP /* DHCP Support */
129	#define CONFIG_CMD_FAT /* FAT support */
130	#define CONFIG_CMD_I2C /* I2C serial bus support */
131	#define CONFIG_CMD_IDE /* IDE harddisk support */
132	#define CONFIG_CMD_IRQ /* irqinfo */
133	#define CONFIG_CMD_MII /* MII support */
134	#define CONFIG_CMD_PCI /* pciinfo */
135	#define CONFIG_CMD_USB /* USB Support */
136
137	#define CONFIG_SYS_LOWBOOT 1
138
139	/*
140	* Autobooting
141	*/
142	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143
144	#define CONFIG_PREBOOT "echo;" \
145	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
146	"echo"
147
148	#undef CONFIG_BOOTARGS
149
150	#define CONFIG_EXTRA_ENV_SETTINGS \
151	"netdev=eth0\0" \
152	"consoledev=ttyPSC0\0" \
153	"hostname=ipek01\0" \
154	"nfsargs=setenv bootargs root=/dev/nfs rw " \
155	"nfsroot=${serverip}:${rootpath}\0" \
156	"ramargs=setenv bootargs root=/dev/ram rw\0" \
157	"addip=setenv bootargs ${bootargs} " \
158	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
159	":${hostname}:${netdev}:off panic=1\0" \
160	"addtty=setenv bootargs ${bootargs} " \
161	"console=${consoledev},${baudrate}\0" \
162	"flash_nfs=run nfsargs addip addtty;" \
163	"bootm ${kernel_addr} - ${fdtaddr}\0" \
164	"flash_self=run ramargs addip addtty;" \
165	"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
166	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
167	"run nfsargs addip addtty;" \
168	"bootm ${loadaddr} - ${fdtaddr}\0" \
169	"rootpath=/opt/eldk/ppc_6xx\0" \
170	"bootfile=ipek01/uImage\0" \
171	"load=tftp 100000 ipek01/u-boot.bin\0" \
172	"update=protect off FC000000 +60000; era FC000000 +60000; " \
173	"cp.b 100000 FC000000 ${filesize}\0" \
174	"upd=run load;run update\0" \
175	"fdtaddr=800000\0" \
176	"loadaddr=400000\0" \
177	"fdtfile=ipek01/ipek01.dtb\0" \
178	""
179
180	#define CONFIG_BOOTCOMMAND "run flash_self"
181
182	/*
183	* IPB Bus clocking configuration.
184	*/
185	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
186	/* PCI clock must be 33, because board will not boot */
187	#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
188
189	/*
190	* Open firmware flat tree support
191	*/
192	#define CONFIG_OF_LIBFDT 1
193	#define CONFIG_OF_BOARD_SETUP 1
194
195	#define OF_CPU "PowerPC,5200@0"
196	#define OF_SOC "soc5200@f0000000"
197	#define OF_TBCLK (bd->bi_busfreq / 4)
198
199	/*
200	* I2C configuration
201	*/
202	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
203	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
204
205	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
206	#define CONFIG_SYS_I2C_SLAVE 0x7F
207
208	/*
209	* EEPROM configuration
210	*/
211	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
212	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
213	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
214	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
215
216	/*
217	* RTC configuration
218	*/
219	#define CONFIG_RTC_PCF8563
220	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
221
222	#define CONFIG_SYS_FLASH_BASE 0xFC000000
223	#define CONFIG_SYS_FLASH_SIZE 0x01000000
224	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
225	CONFIG_SYS_MONITOR_LEN)
226
227	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
228	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
229	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
230
231	/* use CFI flash driver */
232	#define CONFIG_FLASH_CFI_DRIVER
233	#define CONFIG_SYS_FLASH_CFI
234	#define CONFIG_SYS_FLASH_EMPTY_INFO
235	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
236
237	/*
238	* Environment settings
239	*/
240	#define CONFIG_ENV_IS_IN_FLASH 1
241	#define CONFIG_ENV_SIZE 0x10000
242	#define CONFIG_ENV_SECT_SIZE 0x20000
243	#define CONFIG_ENV_OVERWRITE 1
244	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
245	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
246
247	/*
248	* Memory map
249	*/
250	#define CONFIG_SYS_MBAR 0xf0000000
251	#define CONFIG_SYS_SDRAM_BASE 0x00000000
252	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
253	#define CONFIG_SYS_SRAM_BASE 0xF1000000
254	#define CONFIG_SYS_SRAM_SIZE 0x00200000
255	#define CONFIG_SYS_LIME_BASE 0xE4000000
256	#define CONFIG_SYS_LIME_SIZE 0x04000000
257	#define CONFIG_SYS_FPGA_BASE 0xC0000000
258	#define CONFIG_SYS_FPGA_SIZE 0x10000000
259	#define CONFIG_SYS_MPEG_BASE 0xe2000000
260	#define CONFIG_SYS_MPEG_SIZE 0x01000000
261	#define CONFIG_SYS_CF_BASE 0xe1000000
262	#define CONFIG_SYS_CF_SIZE 0x01000000
263
264	/* Use SRAM until RAM will be available */
265	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
266	/* End of used area in DPRAM */
267	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
268
cd12f615 WG	269	/* size in bytes reserved for initial data */
	270	#define CONFIG_SYS_GBL_DATA_SIZE 128
	271
	272	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
	273	CONFIG_SYS_GBL_DATA_SIZE)
	274	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	275
14d0a02a	276	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
cd12f615 WG	277	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	278	# define CONFIG_SYS_RAMBOOT 1
	279	#endif
	280
	281	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	282	#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
	283	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	284
	285	/*
	286	* Ethernet configuration
	287	*/
	288	#define CONFIG_MPC5xxx_FEC 1
	289	#define CONFIG_MPC5xxx_FEC_MII100
	290	#define CONFIG_PHY_ADDR 0x00
	291
	292	/*
	293	* GPIO configuration
	294	*/
	295	#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
	296
	297	/*
	298	* Miscellaneous configurable options
	299	*/
	300	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	301	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	302	#ifdef CONFIG_CMD_KGDB
	303	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	304	#else
	305	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	306	#endif
	307	/* Print Buffer Size */
	308	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	309	sizeof(CONFIG_SYS_PROMPT) + 16)
	310	/* max number of command args */
	311	#define CONFIG_SYS_MAXARGS 16
	312	/* Boot Argument Buffer Size */
	313	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	314
cd12f615 WG	315	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	316	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
	317
	318	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	319
	320	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
	321	#define CONFIG_LOOPW
	322
	323	/*
	324	* Various low-level settings
	325	*/
cd12f615 WG	326	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
cd12f615 WG	327	#define CONFIG_SYS_HID0_FINAL HID0_ICE
cd12f615 WG	328
	329	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	330	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	331	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	332	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	333	#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
	334	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
	335	#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
	336	#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
	337	#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
	338	#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
	339	#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
	340	#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
	341	#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
	342	#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
	343
	344	#ifdef CONFIG_SYS_PCISPEED_66
	345	#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
	346	#define CONFIG_SYS_CS1_CFG 0x0004FB00
	347	#define CONFIG_SYS_CS2_CFG 0x0006F900
	348	#else
	349	#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
	350	#define CONFIG_SYS_CS1_CFG 0x0001FB00
	351	#define CONFIG_SYS_CS2_CFG 0x0002F90C
	352	#endif
	353
	354	/*
	355	* Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
	356	* waitstates, writeswap and readswap enabled
	357	*/
	358	#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
	359	#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
	360	#define CONFIG_SYS_CS7_CFG 0x4040751C
	361
	362	#define CONFIG_SYS_CS_BURST 0x00000000
	363	#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
	364
	365	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
	366
	367	/*-----------------------------------------------------------------------
	368	* USB stuff
	369	*-----------------------------------------------------------------------
	370	*/
	371	#define CONFIG_USB_CLOCK 0x0001BBBB
	372	#define CONFIG_USB_CONFIG 0x00005000
	373
	374	/*-----------------------------------------------------------------------
	375	* IDE/ATA stuff Supports IDE harddisk
	376	*-----------------------------------------------------------------------
	377	*/
	378	#define CONFIG_IDE_PREINIT
	379
	380	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	381	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
	382
	383	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	384
	385	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	386
	387	/* Offset for data I/O */
	388	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	389
	390	/* Offset for normal register accesses */
	391	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
392
393	/* Offset for alternate registers */
394	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
395
396	/* Interval between registers */
397	#define CONFIG_SYS_ATA_STRIDE 4
398
399	#endif /* __CONFIG_H */