[people/ms/u-boot.git] / include / configs / jupiter.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* especially an MPC5200 */
#define CONFIG_JUPITER		1	/* ... on Jupiter board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFF00000	boot high (standard configuration)
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_BOARD_EARLY_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F	1

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
/*#define CONFIG_PCI		*/

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#if defined(CONFIG_PCI)
#define CODFIG_CMD_PCI
#endif


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
		"${baudrate}\0"						\
	"contyp=ttyS0\0"						\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/jupiter/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */

#if 0
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 8)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
#endif

#if 0
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
#define CONFIG_SYS_ALT_MEMTEST		1

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
2605e90b HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* especially an MPC5200 */
	34	#define CONFIG_JUPITER 1 /* ... on Jupiter board */
	35
2ae18241 WD	36	/*
	37	* Valid values for CONFIG_SYS_TEXT_BASE are:
	38	* 0xFFF00000 boot high (standard configuration)
	39	* 0x00100000 boot from RAM (for testing only)
	40	*/
	41	#ifndef CONFIG_SYS_TEXT_BASE
	42	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	43	#endif
	44
6d0f6bcf	45	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
2605e90b HS	46
	47	#define CONFIG_BOARD_EARLY_INIT_R 1
	48	#define CONFIG_BOARD_EARLY_INIT_F 1
	49
31d82672 BB	50	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	51
2605e90b HS	52	/*
	53	* Serial console configuration
	54	*/
	55	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	56	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	57	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
2605e90b HS	58
	59	/*
	60	* PCI Mapping:
	61	* 0x40000000 - 0x4fffffff - PCI Memory
	62	* 0x50000000 - 0x50ffffff - PCI IO Space
	63	*/
769104c9	64	/#define CONFIG_PCI /
2605e90b HS	65
	66	#if defined(CONFIG_PCI)
	67	#define CONFIG_PCI_PNP 1
	68	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	69	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2605e90b HS	70
	71	#define CONFIG_PCI_MEM_BUS 0x40000000
	72	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	73	#define CONFIG_PCI_MEM_SIZE 0x10000000
	74
	75	#define CONFIG_PCI_IO_BUS 0x50000000
	76	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	77	#define CONFIG_PCI_IO_SIZE 0x01000000
2605e90b HS	78	#endif
2605e90b HS	79
6d0f6bcf	80	#define CONFIG_SYS_XLB_PIPELINING 1
2605e90b HS	81
	82	#define CONFIG_NET_MULTI 1
	83	#define CONFIG_MII 1
6d0f6bcf	84	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
2605e90b HS	85
	86	/* Partitions */
	87	#define CONFIG_MAC_PARTITION
	88	#define CONFIG_DOS_PARTITION
	89	#define CONFIG_ISO_PARTITION
	90
	91	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	92
bc234c12	93
7f5c0157 JL	94	/*
	95	* BOOTP options
	96	*/
	97	#define CONFIG_BOOTP_BOOTFILESIZE
	98	#define CONFIG_BOOTP_BOOTPATH
	99	#define CONFIG_BOOTP_GATEWAY
	100	#define CONFIG_BOOTP_HOSTNAME
	101
	102
2605e90b	103	/*
bc234c12	104	* Command line configuration.
2605e90b	105	*/
bc234c12 JL	106	#include <config_cmd_default.h>
	107
	108	#define CONFIG_CMD_NFS
	109	#define CONFIG_CMD_SNTP
2605e90b	110
7f5c0157 JL	111	#if defined(CONFIG_PCI)
	112	#define CODFIG_CMD_PCI
	113	#endif
	114
2605e90b HS	115
	116	/*
	117	* Autobooting
	118	*/
	119	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	120
	121	#define CONFIG_PREBOOT "echo;" \
32bf3d14	122	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
2605e90b HS	123	"echo"
	124
	125	#undef CONFIG_BOOTARGS
	126
	127	#define CONFIG_EXTRA_ENV_SETTINGS \
	128	"netdev=eth0\0" \
	129	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	130	"nfsroot=${serverip}:${rootpath}\0" \
	131	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	132	"addip=setenv bootargs ${bootargs} " \
	133	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	134	":${hostname}:${netdev}:off panic=1\0" \
a7090b99	135	"flash_nfs=run nfsargs addip addcons;" \
2605e90b HS	136	"bootm ${kernel_addr}\0" \
	137	"flash_self=run ramargs addip;" \
	138	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
a7090b99	139	"addcons=setenv bootargs ${bootargs} console=${contyp}," \
8502e30a HS	140	"${baudrate}\0" \
8502e30a HS	141	"contyp=ttyS0\0" \
a7090b99	142	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
8502e30a HS	143	"bootm\0" \
8502e30a HS	144	"rootpath=/opt/eldk/ppc_6xx\0" \
2605e90b HS	145	"bootfile=/tftpboot/jupiter/uImage\0" \
	146	""
	147
	148	#define CONFIG_BOOTCOMMAND "run flash_self"
	149
	150	/*
	151	* IPB Bus clocking configuration.
	152	*/
6d0f6bcf	153	#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
2605e90b HS	154
	155	#if 0
	156	/* pass open firmware flat tree */
cf2817a8	157	#define CONFIG_OF_LIBFDT 1
2605e90b HS	158	#define CONFIG_OF_BOARD_SETUP 1
2605e90b HS	159
2605e90b HS	160	#define OF_CPU "PowerPC,5200@0"
	161	#define OF_SOC "soc5200@f0000000"
	162	#define OF_TBCLK (bd->bi_busfreq / 8)
	163	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	164	#endif
	165
	166	#if 0
	167	/*
	168	* I2C configuration
	169	*/
	170	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	171	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
2605e90b	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	174	#define CONFIG_SYS_I2C_SLAVE 0x7F
2605e90b HS	175
	176	/*
	177	* EEPROM configuration
	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	180	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	181	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	182	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
2605e90b HS	183	#endif
	184
	185	/*
	186	* Flash configuration
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_SIZE 0x01000000
2605e90b	190
6d0f6bcf	191	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
2605e90b	192
14d0a02a	193	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
2605e90b	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	196	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
2605e90b	197
6d0f6bcf	198	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
2605e90b	199
00b1883a	200	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_CFI
	202	#define CONFIG_SYS_FLASH_EMPTY_INFO
	203	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	204	#define CONFIG_SYS_UPDATE_FLASH_SIZE 1
	205	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
2605e90b HS	206
	207	/*
	208	* Environment settings
	209	*/
5a1aceb0	210	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	211	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	212	#define CONFIG_ENV_SECT_SIZE 0x20000
2605e90b HS	213	#define CONFIG_ENV_OVERWRITE 1
2605e90b HS	214
8502e30a	215	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	216	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	217	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
8502e30a	218
2605e90b HS	219	/*
	220	* Memory map
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_MBAR 0xF0000000
	223	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	224	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
2605e90b HS	225
2605e90b HS	226	/* Use SRAM until RAM will be available */
6d0f6bcf	227	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	228	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
2605e90b HS	229
2605e90b HS	230
6d0f6bcf	231	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
553f0982	232	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	233	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
2605e90b	234
14d0a02a	235	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	236	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	237	# define CONFIG_SYS_RAMBOOT 1
2605e90b HS	238	#endif
2605e90b HS	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	241	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	242	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
2605e90b HS	243
	244	/*
	245	* Ethernet configuration
	246	*/
	247	#define CONFIG_MPC5xxx_FEC 1
86321fc1	248	#define CONFIG_MPC5xxx_FEC_MII100
2605e90b	249	/*
86321fc1	250	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
2605e90b	251	*/
86321fc1	252	/* #define CONFIG_MPC5xxx_FEC_MII10 */
2605e90b HS	253	#define CONFIG_PHY_ADDR 0x00
	254
	255	/*
	256	* GPIO configuration
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
2605e90b HS	259
	260	/*
	261	* Miscellaneous configurable options
	262	*/
6d0f6bcf JCPV	263	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	264	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
8502e30a HS	265
8502e30a HS	266	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf JCPV	267	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
	268	#ifdef CONFIG_SYS_HUSH_PARSER
	269	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
8502e30a	270	#endif
bc234c12	271	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	272	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
2605e90b	273	#else
6d0f6bcf	274	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
2605e90b	275	#endif
6d0f6bcf JCPV	276	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	277	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	278	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
2605e90b	279
6d0f6bcf JCPV	280	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	281	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	282	#define CONFIG_SYS_ALT_MEMTEST 1
2605e90b	283
6d0f6bcf	284	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
2605e90b	285
6d0f6bcf	286	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
2605e90b	287
6d0f6bcf	288	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
bc234c12	289	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	290	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
bc234c12 JL	291	#endif
bc234c12 JL	292
2605e90b HS	293	/*
	294	* Various low-level settings
	295	*/
6d0f6bcf JCPV	296	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	297	#define CONFIG_SYS_HID0_FINAL HID0_ICE
2605e90b	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	300	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	301	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	302	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	303	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
2605e90b	304
6d0f6bcf JCPV	305	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	306	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
2605e90b	307
6d0f6bcf	308	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
2605e90b HS	309
2605e90b HS	310	#endif /* __CONFIG_H */