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4745acaa SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /************************************************************************ | |
27 | * katmai.h - configuration for AMCC Katmai (440SPe) | |
28 | ***********************************************************************/ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
83b4cfa3 | 32 | |
4745acaa SR |
33 | /*----------------------------------------------------------------------- |
34 | * High Level Configuration Options | |
35 | *----------------------------------------------------------------------*/ | |
36 | #define CONFIG_KATMAI 1 /* Board is Katmai */ | |
37 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
38 | #define CONFIG_440 1 /* ... PPC440 family */ | |
39 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
4745acaa | 40 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
490f2040 SR |
41 | #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
42 | ||
43 | /* | |
44 | * Include common defines/options for all AMCC eval boards | |
45 | */ | |
46 | #define CONFIG_HOSTNAME katmai | |
47 | #include "amcc-common.h" | |
4745acaa SR |
48 | |
49 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
50 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ | |
4745acaa SR |
51 | #undef CONFIG_SHOW_BOOT_PROGRESS |
52 | ||
53 | /*----------------------------------------------------------------------- | |
54 | * Base addresses -- Note these are effective addresses where the | |
55 | * actual resources get mapped (not physical addresses) | |
56 | *----------------------------------------------------------------------*/ | |
4745acaa | 57 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ |
4745acaa SR |
58 | #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ |
59 | #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ | |
60 | ||
61 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ | |
62 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
63 | #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE | |
64 | ||
65 | #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ | |
4dbee8a9 | 66 | #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ |
4745acaa SR |
67 | #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ |
68 | ||
69 | #define CFG_PCIE0_CFGBASE 0xc0000000 | |
7f191393 GB |
70 | #define CFG_PCIE1_CFGBASE 0xc1000000 |
71 | #define CFG_PCIE2_CFGBASE 0xc2000000 | |
72 | #define CFG_PCIE0_XCFGBASE 0xc3000000 | |
73 | #define CFG_PCIE1_XCFGBASE 0xc3001000 | |
74 | #define CFG_PCIE2_XCFGBASE 0xc3002000 | |
4745acaa | 75 | |
97923770 | 76 | /* base address of inbound PCIe window */ |
c36c6816 | 77 | #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL |
97923770 | 78 | |
4745acaa SR |
79 | /* System RAM mapped to PCI space */ |
80 | #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE | |
81 | #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE | |
82 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
83 | ||
a65c5768 | 84 | #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ |
4745acaa SR |
85 | |
86 | /*----------------------------------------------------------------------- | |
87 | * Initial RAM & stack pointer (placed in internal SRAM) | |
88 | *----------------------------------------------------------------------*/ | |
89 | #define CFG_TEMP_STACK_OCM 1 | |
90 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
91 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ | |
92 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
93 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
94 | ||
95 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
96 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
97 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
98 | ||
99 | /*----------------------------------------------------------------------- | |
100 | * Serial Port | |
101 | *----------------------------------------------------------------------*/ | |
4745acaa SR |
102 | #undef CONFIG_UART1_CONSOLE |
103 | #undef CFG_EXT_SERIAL_CLOCK | |
4745acaa SR |
104 | |
105 | /*----------------------------------------------------------------------- | |
106 | * DDR SDRAM | |
107 | *----------------------------------------------------------------------*/ | |
108 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ | |
ba58e4c9 | 109 | #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ |
2721a68a | 110 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
845c6c95 | 111 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/ |
4745acaa | 112 | #undef CONFIG_STRESS |
4745acaa SR |
113 | |
114 | /*----------------------------------------------------------------------- | |
115 | * I2C | |
116 | *----------------------------------------------------------------------*/ | |
4745acaa | 117 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
4745acaa SR |
118 | |
119 | #define CONFIG_I2C_MULTI_BUS | |
120 | #define CONFIG_I2C_CMD_TREE | |
121 | #define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */ | |
122 | ||
123 | #define IIC0_BOOTPROM_ADDR 0x50 | |
124 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 | |
125 | ||
126 | #define CFG_I2C_MULTI_EEPROMS | |
127 | #define CFG_I2C_EEPROM_ADDR (0x50) | |
128 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
129 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
130 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
131 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
132 | ||
133 | /* I2C RTC */ | |
134 | #define CONFIG_RTC_M41T11 1 | |
135 | #define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */ | |
136 | #define CFG_I2C_RTC_ADDR 0x68 | |
137 | #define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
138 | ||
139 | /* I2C DTT */ | |
140 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ | |
141 | #define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */ | |
142 | /* | |
143 | * standard dtt sensor configuration - bottom bit will determine local or | |
144 | * remote sensor of the ADM1021, the rest determines index into | |
145 | * CFG_DTT_ADM1021 array below. | |
146 | */ | |
147 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
148 | ||
149 | /* | |
150 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). | |
151 | * there will be one entry in this array for each two (dummy) sensors in | |
152 | * CONFIG_DTT_SENSORS. | |
153 | * | |
154 | * For Katmai board: | |
155 | * - only one ADM1021 | |
156 | * - i2c addr 0x18 | |
157 | * - conversion rate 0x02 = 0.25 conversions/second | |
158 | * - ALERT ouput disabled | |
159 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
160 | * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg | |
161 | */ | |
162 | #define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } | |
163 | ||
164 | /*----------------------------------------------------------------------- | |
165 | * Environment | |
166 | *----------------------------------------------------------------------*/ | |
167 | #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ | |
168 | ||
490f2040 SR |
169 | /* |
170 | * Default environment variables | |
171 | */ | |
4745acaa | 172 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
173 | CONFIG_AMCC_DEF_ENV \ |
174 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
175 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
176 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
4745acaa SR |
177 | "kernel_addr=fff10000\0" \ |
178 | "ramdisk_addr=fff20000\0" \ | |
4745acaa | 179 | "kozio=bootm ffc60000\0" \ |
6efc1fc0 | 180 | "pciconfighost=1\0" \ |
d4cb2d17 | 181 | "pcie_mode=RP:RP:RP\0" \ |
4745acaa | 182 | "" |
079a136c | 183 | |
bc234c12 | 184 | /* |
490f2040 | 185 | * Commands additional to the ones defined in amcc-common.h |
bc234c12 | 186 | */ |
bc234c12 | 187 | #define CONFIG_CMD_DATE |
bc234c12 | 188 | #define CONFIG_CMD_PCI |
bc234c12 | 189 | #define CONFIG_CMD_SDRAM |
afe9fa59 | 190 | #define CONFIG_CMD_SNTP |
4745acaa SR |
191 | |
192 | #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ | |
4745acaa SR |
193 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
194 | #define CONFIG_HAS_ETH0 | |
195 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
196 | #define CONFIG_PHY_RESET_DELAY 1000 | |
197 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
198 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
4745acaa SR |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * FLASH related | |
202 | *----------------------------------------------------------------------*/ | |
203 | #define CFG_FLASH_CFI | |
204 | #define CFG_FLASH_CFI_DRIVER | |
205 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
206 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
207 | ||
208 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} | |
209 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
210 | #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ | |
211 | ||
212 | #undef CFG_FLASH_CHECKSUM | |
213 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
214 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
215 | ||
216 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
217 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) | |
218 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
219 | ||
220 | /* Address and size of Redundant Environment Sector */ | |
221 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
222 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
223 | ||
224 | /*----------------------------------------------------------------------- | |
225 | * PCI stuff | |
226 | *----------------------------------------------------------------------- | |
227 | */ | |
228 | /* General PCI */ | |
229 | #define CONFIG_PCI /* include pci support */ | |
230 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
231 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
6efc1fc0 | 232 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE |
4745acaa SR |
233 | |
234 | /* Board-specific PCI */ | |
4745acaa SR |
235 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
236 | #undef CFG_PCI_MASTER_INIT | |
237 | ||
238 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
239 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
240 | /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ | |
241 | ||
242 | /* | |
243 | * NETWORK Support (PCI): | |
244 | */ | |
245 | /* Support for Intel 82557/82559/82559ER chips. */ | |
246 | #define CONFIG_EEPRO100 | |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * Xilinx System ACE support | |
250 | *----------------------------------------------------------------------*/ | |
251 | #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ | |
252 | #define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ | |
253 | #define CFG_SYSTEMACE_BASE CFG_ACE_BASE | |
254 | #define CONFIG_DOS_PARTITION 1 | |
255 | ||
256 | /*----------------------------------------------------------------------- | |
257 | * External Bus Controller (EBC) Setup | |
258 | *----------------------------------------------------------------------*/ | |
259 | ||
260 | /* Memory Bank 0 (Flash) initialization */ | |
261 | #define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
262 | EBC_BXAP_TWT_ENCODE(7) | \ | |
263 | EBC_BXAP_BCE_DISABLE | \ | |
264 | EBC_BXAP_BCT_2TRANS | \ | |
265 | EBC_BXAP_CSN_ENCODE(0) | \ | |
266 | EBC_BXAP_OEN_ENCODE(0) | \ | |
267 | EBC_BXAP_WBN_ENCODE(0) | \ | |
268 | EBC_BXAP_WBF_ENCODE(0) | \ | |
269 | EBC_BXAP_TH_ENCODE(0) | \ | |
270 | EBC_BXAP_RE_DISABLED | \ | |
271 | EBC_BXAP_SOR_DELAYED | \ | |
272 | EBC_BXAP_BEM_WRITEONLY | \ | |
273 | EBC_BXAP_PEN_DISABLED) | |
274 | #define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \ | |
275 | EBC_BXCR_BS_16MB | \ | |
276 | EBC_BXCR_BU_RW | \ | |
277 | EBC_BXCR_BW_16BIT) | |
278 | ||
279 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
d2168626 SR |
280 | #define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ |
281 | EBC_BXAP_TWT_ENCODE(4) | \ | |
282 | EBC_BXAP_BCE_DISABLE | \ | |
283 | EBC_BXAP_BCT_2TRANS | \ | |
284 | EBC_BXAP_CSN_ENCODE(0) | \ | |
285 | EBC_BXAP_OEN_ENCODE(0) | \ | |
286 | EBC_BXAP_WBN_ENCODE(0) | \ | |
287 | EBC_BXAP_WBF_ENCODE(0) | \ | |
288 | EBC_BXAP_TH_ENCODE(0) | \ | |
289 | EBC_BXAP_RE_DISABLED | \ | |
290 | EBC_BXAP_SOR_NONDELAYED | \ | |
291 | EBC_BXAP_BEM_WRITEONLY | \ | |
292 | EBC_BXAP_PEN_DISABLED) | |
4745acaa SR |
293 | #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ |
294 | EBC_BXCR_BS_1MB | \ | |
295 | EBC_BXCR_BU_RW | \ | |
296 | EBC_BXCR_BW_16BIT) | |
297 | ||
298 | /*------------------------------------------------------------------------- | |
299 | * Initialize EBC CONFIG - | |
300 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
301 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
302 | *-------------------------------------------------------------------------*/ | |
303 | #define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \ | |
304 | EBC_CFG_PTD_ENABLE | \ | |
305 | EBC_CFG_RTC_16PERCLK | \ | |
306 | EBC_CFG_ATC_PREVIOUS | \ | |
307 | EBC_CFG_DTC_PREVIOUS | \ | |
308 | EBC_CFG_CTC_PREVIOUS | \ | |
309 | EBC_CFG_OEO_PREVIOUS | \ | |
310 | EBC_CFG_EMC_DEFAULT | \ | |
311 | EBC_CFG_PME_DISABLE | \ | |
312 | EBC_CFG_PR_16) | |
313 | ||
ba58e4c9 SR |
314 | /*----------------------------------------------------------------------- |
315 | * GPIO Setup | |
316 | *----------------------------------------------------------------------*/ | |
317 | #define CFG_GPIO_PCIE_PRESENT0 17 | |
318 | #define CFG_GPIO_PCIE_PRESENT1 21 | |
319 | #define CFG_GPIO_PCIE_PRESENT2 23 | |
320 | #define CFG_GPIO_RS232_FORCEOFF 30 | |
321 | ||
322 | #define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \ | |
323 | GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \ | |
324 | GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \ | |
325 | GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)) | |
326 | #define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) | |
327 | #define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) | |
328 | #define CFG_GPIO_ODR 0 | |
329 | ||
4745acaa | 330 | #endif /* __CONFIG_H */ |