projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 566806ca | 1 | /* |
| 8a24c07b GE |
2 | * Copyright (c) 2008 Nuovation System Designs, LLC |
| 3 | * Grant Erickson <gerickson@nuovations.com> | |
| 4 | * | |
| 566806ca SR |
5 | * (C) Copyright 2007 |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | /************************************************************************ | |
| 28 | * kilauea.h - configuration for AMCC Kilauea (405EX) | |
| 29 | ***********************************************************************/ | |
| 30 | ||
| 31 | #ifndef __CONFIG_H | |
| 32 | #define __CONFIG_H | |
| 33 | ||
| 34 | /*----------------------------------------------------------------------- | |
| 35 | * High Level Configuration Options | |
| 36 | *----------------------------------------------------------------------*/ | |
| 37 | #define CONFIG_KILAUEA 1 /* Board is Kilauea */ | |
| 38 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 39 | #define CONFIG_405EX 1 /* Specifc 405EX support*/ | |
| 40 | #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ | |
| 41 | ||
| 490f2040 SR |
42 | /* |
| 43 | * Include common defines/options for all AMCC eval boards | |
| 44 | */ | |
| 45 | #define CONFIG_HOSTNAME kilauea | |
| 46 | #include "amcc-common.h" | |
| 47 | ||
| 566806ca SR |
48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 49 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
| 353f2688 | 50 | #define CONFIG_BOARD_EMAC_COUNT |
| 566806ca SR |
51 | |
| 52 | /*----------------------------------------------------------------------- | |
| 53 | * Base addresses -- Note these are effective addresses where the | |
| 54 | * actual resources get mapped (not physical addresses) | |
| 55 | *----------------------------------------------------------------------*/ | |
| 566806ca SR |
56 | #define CFG_FLASH_BASE 0xFC000000 |
| 57 | #define CFG_NAND_ADDR 0xF8000000 | |
| 58 | #define CFG_FPGA_BASE 0xF0000000 | |
| 59 | #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ | |
| 566806ca SR |
60 | |
| 61 | /*----------------------------------------------------------------------- | |
| 8a24c07b GE |
62 | * Initial RAM & Stack Pointer Configuration Options |
| 63 | * | |
| 64 | * There are traditionally three options for the primordial | |
| 65 | * (i.e. initial) stack usage on the 405-series: | |
| 66 | * | |
| 67 | * 1) On-chip Memory (OCM) (i.e. SRAM) | |
| 68 | * 2) Data cache | |
| 69 | * 3) SDRAM | |
| 70 | * | |
| 71 | * For the 405EX(r), there is no OCM, so we are left with (2) or (3) | |
| 72 | * the latter of which is less than desireable since it requires | |
| 73 | * setting up the SDRAM and ECC in assembly code. | |
| 74 | * | |
| 75 | * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip | |
| 76 | * select on the External Bus Controller (EBC) and then select a | |
| 77 | * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid, | |
| 78 | * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and | |
| 79 | * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid, | |
| 80 | * physical SDRAM to use (3). | |
| 81 | *-----------------------------------------------------------------------*/ | |
| 82 | ||
| 83 | #define CFG_INIT_DCACHE_CS 4 | |
| 84 | ||
| 85 | #if defined(CFG_INIT_DCACHE_CS) | |
| 86 | #define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ | |
| 87 | #else | |
| 88 | #define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */ | |
| 89 | #endif /* defined(CFG_INIT_DCACHE_CS) */ | |
| 90 | ||
| 91 | #define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */ | |
| 566806ca SR |
92 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
| 93 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 566806ca | 94 | |
| 8a24c07b GE |
95 | /* |
| 96 | * If the data cache is being used for the primordial stack and global | |
| 97 | * data area, the POST word must be placed somewhere else. The General | |
| 98 | * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves | |
| 99 | * its compare and mask register contents across reset, so it is used | |
| 100 | * for the POST word. | |
| 101 | */ | |
| 102 | ||
| 103 | #if defined(CFG_INIT_DCACHE_CS) | |
| 104 | # define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 105 | # define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) | |
| 106 | #else | |
| 107 | # define CFG_INIT_EXTRA_SIZE 16 | |
| 108 | # define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE) | |
| 109 | # define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) | |
| 110 | # define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR | |
| 111 | #endif /* defined(CFG_INIT_DCACHE_CS) */ | |
| 566806ca SR |
112 | |
| 113 | /*----------------------------------------------------------------------- | |
| 114 | * Serial Port | |
| 115 | *----------------------------------------------------------------------*/ | |
| 116 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ | |
| 566806ca SR |
117 | /* define this if you want console on UART1 */ |
| 118 | #undef CONFIG_UART1_CONSOLE | |
| 119 | ||
| 566806ca SR |
120 | /*----------------------------------------------------------------------- |
| 121 | * Environment | |
| 122 | *----------------------------------------------------------------------*/ | |
| 123 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
| 124 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
| 125 | #else | |
| 126 | #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ | |
| 127 | #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ | |
| 128 | #endif | |
| 129 | ||
| 130 | /*----------------------------------------------------------------------- | |
| 131 | * FLASH related | |
| 132 | *----------------------------------------------------------------------*/ | |
| 133 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
| 134 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
| 135 | ||
| 136 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} | |
| 137 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 138 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
| 139 | ||
| 140 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 141 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 142 | ||
| 143 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| 144 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
| 145 | ||
| 146 | #ifdef CFG_ENV_IS_IN_FLASH | |
| 53677ef1 | 147 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 566806ca SR |
148 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
| 149 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
| 150 | ||
| 151 | /* Address and size of Redundant Environment Sector */ | |
| 152 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
| 153 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
| 154 | #endif /* CFG_ENV_IS_IN_FLASH */ | |
| 155 | ||
| 3d6cb3b2 SR |
156 | /* |
| 157 | * IPL (Initial Program Loader, integrated inside CPU) | |
| 158 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
| 159 | * | |
| 160 | * SPL (Secondary Program Loader) | |
| 161 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
| 162 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
| 163 | * controller and the NAND controller so that the special U-Boot image can be | |
| 164 | * loaded from NAND to SDRAM. | |
| 165 | * | |
| 166 | * NUB (NAND U-Boot) | |
| 167 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
| 168 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
| 169 | * | |
| ec724f88 SR |
170 | * On 405EX the SPL is copied to SDRAM before the NAND controller is |
| 171 | * set up. While still running from location 0xfffff000...0xffffffff the | |
| 172 | * NAND controller cannot be accessed since it is attached to CS0 too. | |
| 3d6cb3b2 SR |
173 | */ |
| 174 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ | |
| 175 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
| 176 | #define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
| 177 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
| 178 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
| 179 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) | |
| 180 | ||
| 181 | /* | |
| 182 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
| 183 | */ | |
| 184 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ | |
| 185 | #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
| 186 | ||
| 187 | /* | |
| 188 | * Now the NAND chip has to be defined (no autodetection used!) | |
| 189 | */ | |
| 190 | #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ | |
| 191 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
| 192 | #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
| 193 | #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
| 194 | #define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
| 195 | ||
| 196 | #define CFG_NAND_ECCSIZE 256 | |
| 197 | #define CFG_NAND_ECCBYTES 3 | |
| 198 | #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) | |
| 199 | #define CFG_NAND_OOBSIZE 16 | |
| 200 | #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) | |
| 201 | #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
| 202 | ||
| 203 | #ifdef CFG_ENV_IS_IN_NAND | |
| 204 | /* | |
| 205 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
| 206 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
| 207 | */ | |
| 208 | #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE | |
| 209 | #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) | |
| 210 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) | |
| 211 | #endif | |
| 212 | ||
| 213 | /*----------------------------------------------------------------------- | |
| 214 | * NAND FLASH | |
| 215 | *----------------------------------------------------------------------*/ | |
| 216 | #define CFG_MAX_NAND_DEVICE 1 | |
| 217 | #define NAND_MAX_CHIPS 1 | |
| 218 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) | |
| 219 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
| 220 | ||
| 566806ca SR |
221 | /*----------------------------------------------------------------------- |
| 222 | * DDR SDRAM | |
| 223 | *----------------------------------------------------------------------*/ | |
| 224 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ | |
| 225 | ||
| 8a24c07b GE |
226 | #define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) |
| 227 | ||
| 228 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
| 229 | #define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \ | |
| 230 | SDRAM_RXBAS_SDSZ_256MB | \ | |
| 231 | SDRAM_RXBAS_SDAM_MODE7 | \ | |
| 232 | SDRAM_RXBAS_SDBE_ENABLE) | |
| 233 | #define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE | |
| 234 | #define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE | |
| 235 | #define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE | |
| 236 | #define CFG_SDRAM0_MCOPT1 0x04322000 | |
| 237 | #define CFG_SDRAM0_MCOPT2 0x00000000 | |
| 238 | #define CFG_SDRAM0_MODT0 0x01800000 | |
| 239 | #define CFG_SDRAM0_MODT1 0x00000000 | |
| 240 | #define CFG_SDRAM0_CODT 0x0080f837 | |
| 241 | #define CFG_SDRAM0_RTR 0x06180000 | |
| 242 | #define CFG_SDRAM0_INITPLR0 0xa8380000 | |
| 243 | #define CFG_SDRAM0_INITPLR1 0x81900400 | |
| 244 | #define CFG_SDRAM0_INITPLR2 0x81020000 | |
| 245 | #define CFG_SDRAM0_INITPLR3 0x81030000 | |
| 246 | #define CFG_SDRAM0_INITPLR4 0x81010404 | |
| 247 | #define CFG_SDRAM0_INITPLR5 0x81000542 | |
| 248 | #define CFG_SDRAM0_INITPLR6 0x81900400 | |
| 249 | #define CFG_SDRAM0_INITPLR7 0x8D080000 | |
| 250 | #define CFG_SDRAM0_INITPLR8 0x8D080000 | |
| 251 | #define CFG_SDRAM0_INITPLR9 0x8D080000 | |
| 252 | #define CFG_SDRAM0_INITPLR10 0x8D080000 | |
| 253 | #define CFG_SDRAM0_INITPLR11 0x81000442 | |
| 254 | #define CFG_SDRAM0_INITPLR12 0x81010780 | |
| 255 | #define CFG_SDRAM0_INITPLR13 0x81010400 | |
| 256 | #define CFG_SDRAM0_INITPLR14 0x00000000 | |
| 257 | #define CFG_SDRAM0_INITPLR15 0x00000000 | |
| 258 | #define CFG_SDRAM0_RQDC 0x80000038 | |
| 259 | #define CFG_SDRAM0_RFDC 0x00000209 | |
| 260 | #define CFG_SDRAM0_RDCC 0x40000000 | |
| 261 | #define CFG_SDRAM0_DLCR 0x030000a5 | |
| 262 | #define CFG_SDRAM0_CLKTR 0x80000000 | |
| 263 | #define CFG_SDRAM0_WRDTR 0x00000000 | |
| 264 | #define CFG_SDRAM0_SDTR1 0x80201000 | |
| 265 | #define CFG_SDRAM0_SDTR2 0x32204232 | |
| 266 | #define CFG_SDRAM0_SDTR3 0x080b0d1a | |
| 267 | #define CFG_SDRAM0_MMODE 0x00000442 | |
| 268 | #define CFG_SDRAM0_MEMODE 0x00000404 | |
| 269 | ||
| 566806ca SR |
270 | /*----------------------------------------------------------------------- |
| 271 | * I2C | |
| 272 | *----------------------------------------------------------------------*/ | |
| 566806ca | 273 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 566806ca SR |
274 | |
| 275 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ | |
| 276 | #define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ | |
| 277 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
| 278 | ||
| 279 | /* Standard DTT sensor configuration */ | |
| 280 | #define CONFIG_DTT_DS1775 1 | |
| 281 | #define CONFIG_DTT_SENSORS { 0 } | |
| 282 | #define CFG_I2C_DTT_ADDR 0x48 | |
| 283 | ||
| 284 | /* RTC configuration */ | |
| 285 | #define CONFIG_RTC_DS1338 1 | |
| 286 | #define CFG_I2C_RTC_ADDR 0x68 | |
| 287 | ||
| 288 | /*----------------------------------------------------------------------- | |
| 289 | * Ethernet | |
| 290 | *----------------------------------------------------------------------*/ | |
| 291 | #define CONFIG_M88E1111_PHY 1 | |
| 292 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 566806ca SR |
293 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
| 294 | ||
| 295 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 296 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 297 | ||
| 298 | #define CONFIG_HAS_ETH0 1 | |
| 299 | ||
| 566806ca SR |
300 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 301 | #define CONFIG_PHY1_ADDR 2 | |
| 302 | ||
| 490f2040 SR |
303 | /* |
| 304 | * Default environment variables | |
| 305 | */ | |
| 566806ca | 306 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 490f2040 SR |
307 | CONFIG_AMCC_DEF_ENV \ |
| 308 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 309 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
| 310 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 311 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
| 566806ca | 312 | "logversion=2\0" \ |
| 566806ca | 313 | "kernel_addr=fc000000\0" \ |
| 64e541f4 | 314 | "fdt_addr=fc1e0000\0" \ |
| 566806ca | 315 | "ramdisk_addr=fc200000\0" \ |
| 566806ca | 316 | "pciconfighost=1\0" \ |
| d4cb2d17 | 317 | "pcie_mode=RP:RP\0" \ |
| 566806ca | 318 | "" |
| 566806ca SR |
319 | |
| 320 | /* | |
| 490f2040 | 321 | * Commands additional to the ones defined in amcc-common.h |
| 566806ca | 322 | */ |
| 566806ca | 323 | #define CONFIG_CMD_DATE |
| 566806ca | 324 | #define CONFIG_CMD_LOG |
| 566806ca | 325 | #define CONFIG_CMD_NAND |
| 566806ca | 326 | #define CONFIG_CMD_PCI |
| afe9fa59 | 327 | #define CONFIG_CMD_SNTP |
| 566806ca SR |
328 | |
| 329 | /* POST support */ | |
| 8a24c07b | 330 | #define CONFIG_POST (CFG_POST_CACHE | \ |
| 566806ca SR |
331 | CFG_POST_CPU | \ |
| 332 | CFG_POST_ETHER | \ | |
| 333 | CFG_POST_I2C | \ | |
| 334 | CFG_POST_MEMORY | \ | |
| 335 | CFG_POST_UART) | |
| 336 | ||
| 337 | /* Define here the base-addresses of the UARTs to test in POST */ | |
| 338 | #define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE} | |
| 339 | ||
| 340 | #define CONFIG_LOGBUFFER | |
| 341 | #define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ | |
| 342 | ||
| 343 | #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
| 344 | ||
| 566806ca SR |
345 | /*----------------------------------------------------------------------- |
| 346 | * PCI stuff | |
| 347 | *----------------------------------------------------------------------*/ | |
| 348 | #define CONFIG_PCI /* include pci support */ | |
| 349 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
| 350 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
| 351 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
| 352 | ||
| 353 | /*----------------------------------------------------------------------- | |
| 354 | * PCIe stuff | |
| 355 | *----------------------------------------------------------------------*/ | |
| 356 | #define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ | |
| 357 | #define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ | |
| 358 | ||
| 359 | #define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */ | |
| 360 | #define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */ | |
| 361 | #define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ | |
| 362 | ||
| 363 | #define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */ | |
| 364 | #define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */ | |
| 365 | #define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ | |
| 366 | ||
| 367 | #define CFG_PCIE0_UTLBASE 0xef502000 | |
| 368 | #define CFG_PCIE1_UTLBASE 0xef503000 | |
| 369 | ||
| 370 | /* base address of inbound PCIe window */ | |
| 371 | #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL | |
| 372 | ||
| 566806ca SR |
373 | /*----------------------------------------------------------------------- |
| 374 | * External Bus Controller (EBC) Setup | |
| 375 | *----------------------------------------------------------------------*/ | |
| 3d6cb3b2 SR |
376 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| 377 | /* booting from NAND, so NAND chips select has to be on CS 0 */ | |
| 378 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ | |
| 379 | ||
| 380 | /* Memory Bank 1 (NOR-FLASH) initialization */ | |
| 381 | #define CFG_EBC_PB1AP 0x05806500 | |
| 382 | #define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
| 383 | ||
| 384 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
| 385 | #define CFG_EBC_PB0AP 0x018003c0 | |
| 386 | #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000) | |
| 387 | #else | |
| 566806ca SR |
388 | #define CFG_NAND_CS 1 /* NAND chip connected to CSx */ |
| 389 | ||
| 390 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
| 391 | #define CFG_EBC_PB0AP 0x05806500 | |
| 392 | #define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
| 393 | ||
| 394 | /* Memory Bank 1 (NAND-FLASH) initialization */ | |
| 395 | #define CFG_EBC_PB1AP 0x018003c0 | |
| 396 | #define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000) | |
| 3d6cb3b2 | 397 | #endif |
| 566806ca SR |
398 | |
| 399 | /* Memory Bank 2 (FPGA) initialization */ | |
| 400 | #define CFG_EBC_PB2AP 0x9400C800 | |
| ec724f88 | 401 | #define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000) |
| 566806ca SR |
402 | |
| 403 | #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ | |
| 404 | ||
| 566806ca SR |
405 | /*----------------------------------------------------------------------- |
| 406 | * GPIO Setup | |
| 407 | *----------------------------------------------------------------------*/ | |
| 9ea61b57 SR |
408 | #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| 409 | { \ | |
| 410 | /* GPIO Core 0 */ \ | |
| 411 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ | |
| 412 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ | |
| 413 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ | |
| 414 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ | |
| 415 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ | |
| 416 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ | |
| 417 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ | |
| 418 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ | |
| 8be76090 SR |
419 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ |
| 420 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ | |
| 421 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ | |
| 9ea61b57 SR |
422 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ |
| 423 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ | |
| 424 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ | |
| 7cfc12a7 SR |
425 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ |
| 426 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ | |
| 9ea61b57 | 427 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ |
| 8be76090 | 428 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ |
| 9ea61b57 SR |
429 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ |
| 430 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ | |
| 431 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ | |
| 432 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ | |
| 433 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ | |
| 434 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ | |
| 435 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ | |
| 436 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ | |
| 437 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ | |
| 438 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ | |
| 439 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ | |
| 8be76090 SR |
440 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ |
| 441 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ | |
| 442 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ | |
| 9ea61b57 SR |
443 | } \ |
| 444 | } | |
| 566806ca | 445 | |
| 566806ca SR |
446 | /*----------------------------------------------------------------------- |
| 447 | * Some Kilauea stuff..., mainly fpga registers | |
| 448 | */ | |
| 449 | #define CFG_FPGA_REG_BASE CFG_FPGA_BASE | |
| ef264262 | 450 | #define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 10)) |
| 566806ca SR |
451 | |
| 452 | /* interrupt */ | |
| 453 | #define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000 | |
| 454 | #define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000 | |
| 455 | #define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000 | |
| 456 | #define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000 | |
| 457 | #define CFG_FPGA_PHY0_INT 0x08000000 | |
| 458 | #define CFG_FPGA_PHY1_INT 0x04000000 | |
| 459 | #define CFG_FPGA_SLIC0_INT 0x02000000 | |
| 460 | #define CFG_FPGA_SLIC1_INT 0x01000000 | |
| 461 | ||
| 462 | /* DPRAM setting */ | |
| 463 | /* 00: 32B; 01: 64B; 10: 128B; 11: 256B */ | |
| 464 | #define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */ | |
| 465 | #define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */ | |
| 466 | #define CFG_FPGA_DPRAM_RW_TYPE 0x00080000 | |
| 467 | #define CFG_FPGA_DPRAM_RST 0x00040000 | |
| 468 | #define CFG_FPGA_UART0_FO 0x00020000 | |
| 469 | #define CFG_FPGA_UART1_FO 0x00010000 | |
| 470 | ||
| 471 | /* loopback */ | |
| 472 | #define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000 | |
| 473 | #define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000 | |
| 474 | #define CFG_FPGA_SLIC0_ENABLE 0x00002000 | |
| 475 | #define CFG_FPGA_SLIC1_ENABLE 0x00001000 | |
| 476 | #define CFG_FPGA_SLIC0_CS 0x00000800 | |
| 477 | #define CFG_FPGA_SLIC1_CS 0x00000400 | |
| 478 | #define CFG_FPGA_USER_LED0 0x00000200 | |
| 479 | #define CFG_FPGA_USER_LED1 0x00000100 | |
| 480 | ||
| 837c730b | 481 | #endif /* __CONFIG_H */ |