[people/ms/u-boot.git] / include / configs / km_arm.h

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Prafulla Wadaskar <prafulla@marvell.com>
 *
 * (C) Copyright 2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */

#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_MARVELL
#define CONFIG_ARM926EJS		/* Basic Architecture */
#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
#define CONFIG_KIRKWOOD			/* SOC Family Name */
#define CONFIG_KW88F6281		/* SOC Name */
#define CONFIG_MACH_SUEN3		/* Machine type */

/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#undef CONFIG_CMD_DTT
#undef CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
#undef  CONFIG_KIRKWOOD_PCIE_INIT	/* Disable PCIE Port0 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */

#define CONFIG_MISC_INIT_R

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE

/*
 * Serial Port configuration
 * The following definitions let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_CONS_INDEX	1	/* Console on UART0 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG		/* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 	/* enable memory tag */

/*
 * Commands configuration
 */
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS

/*
 * Without NOR FLASH we need this
 */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS

/*
 * NAND Flash configuration
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS			1
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_NAND_BASE		0xd8000000

#define BOOTFLASH_START		0x0

#define CONFIG_KM_CONSOLE_TTY	"ttyS0"

/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128

/*
 * Other required minimal configurations
 */
#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
#define CONFIG_NR_DRAM_BANKS	4
#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */

/*
 * Ethernet Driver configuration
 */
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_NET_MULTI	/* specify more that one ports available */
#define CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
#define CONFIG_PHY_BASE_ADR	0
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */

/*
 * UBI related stuff
 */
#define CONFIG_SYS_USE_UBI

/*
 * I2C related stuff
 */
#define	CONFIG_SOFT_I2C		/* I2C bit-banged	*/

#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
#if defined(CONFIG_SOFT_I2C)
#ifndef __ASSEMBLY__
#include <asm/arch-kirkwood/gpio.h>
extern void __set_direction(unsigned pin, int high);
void set_sda (int state);
void set_scl (int state);
int get_sda (void);
int get_scl (void);
#define SUEN3_SDA_PIN	8
#define SUEN3_SCL_PIN	9
#define SUEN3_ENV_WP	38

#define I2C_ACTIVE	__set_direction(SUEN3_SDA_PIN, 0)
#define I2C_TRISTATE	__set_direction(SUEN3_SDA_PIN, 1)
#define I2C_READ	(kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
#define I2C_SDA(bit)	kw_gpio_set_value(SUEN3_SDA_PIN, bit);
#define I2C_SCL(bit)	kw_gpio_set_value(SUEN3_SCL_PIN, bit);
#endif

#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
#define I2C_SOFT_DECLARATIONS

#define	CONFIG_SYS_I2C_SLAVE		0x0
#define	CONFIG_SYS_I2C_SPEED		100000
#endif

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2

#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
#undef	CONFIG_FLASH_CFI_MTD
#undef	CONFIG_JFFS2_CMDLINE
#endif

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_INIT_SP_ADDR		(0x00000000 + 0x1000 - /* Fix this */ \
					CONFIG_SYS_GBL_DATA_SIZE)
#endif /* _CONFIG_KM_ARM_H */
Commit	Line	Data
67fa8c25 HS	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Prafulla Wadaskar <prafulla@marvell.com>
	5	*
	6	* (C) Copyright 2009
	7	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	25	* MA 02110-1301 USA
	26	*/
	27
	28	/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
	29
	30	#ifndef _CONFIG_KM_ARM_H
	31	#define _CONFIG_KM_ARM_H
	32
	33	/*
	34	* High Level Configuration Options (easy to change)
	35	*/
	36	#define CONFIG_MARVELL
	37	#define CONFIG_ARM926EJS /* Basic Architecture */
	38	#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
	39	#define CONFIG_KIRKWOOD /* SOC Family Name */
	40	#define CONFIG_KW88F6281 /* SOC Name */
	41	#define CONFIG_MACH_SUEN3 /* Machine type */
	42
	43	/* include common defines/options for all Keymile boards */
	44	#include "keymile-common.h"
	45	#undef CONFIG_CMD_DTT
	46	#undef CONFIG_BOOTCOUNT_LIMIT
	47
	48	#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
	49	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
	50	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
	51	#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */
	52	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
	53
	54	#define CONFIG_MISC_INIT_R
	55
	56	/*
	57	* NS16550 Configuration
	58	*/
	59	#define CONFIG_SYS_NS16550
	60	#define CONFIG_SYS_NS16550_SERIAL
	61	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	62	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
	63	#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
	64
65	/*
66	* Serial Port configuration
67	* The following definitions let you select what serial you want to use
68	* for your console driver.
69	*/
70
71	#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
72
73	/*
74	* For booting Linux, the board info and command line data
75	* have to be in the first 8 MB of memory, since this is
76	* the maximum mapped by the Linux kernel during initialization.
77	*/
78	#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
79	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
80	#define CONFIG_INITRD_TAG /* enable INITRD tag */
81	#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
82
83	/*
84	* Commands configuration
85	*/
86	#define CONFIG_CMD_ELF
87	#define CONFIG_CMD_MTDPARTS
88	#define CONFIG_CMD_NAND
89	#define CONFIG_CMD_NFS
90
91	/*
92	* Without NOR FLASH we need this
93	*/
94	#define CONFIG_SYS_NO_FLASH
95	#undef CONFIG_CMD_FLASH
96	#undef CONFIG_CMD_IMLS
97
98	/*
99	* NAND Flash configuration
100	*/
101	#define CONFIG_SYS_MAX_NAND_DEVICE 1
102	#define NAND_MAX_CHIPS 1
103	#define CONFIG_NAND_KIRKWOOD
104	#define CONFIG_SYS_NAND_BASE 0xd8000000
105
106	#define BOOTFLASH_START 0x0
107
108	#define CONFIG_KM_CONSOLE_TTY "ttyS0"
109
110	/* size in bytes reserved for initial data */
111	#define CONFIG_SYS_GBL_DATA_SIZE 128
112
113	/*
114	* Other required minimal configurations
115	*/
116	#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
117	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
118	#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
119	#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
120	#define CONFIG_NR_DRAM_BANKS 4
121	#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
122	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
123
124	/*
125	* Ethernet Driver configuration
126	*/
127	#define CONFIG_NETCONSOLE /* include NetConsole support */
128	#define CONFIG_NET_MULTI /* specify more that one ports available */
129	#define CONFIG_MII /* expose smi ove miiphy interface */
d44265ad	130	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
67fa8c25	131	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
d44265ad	132	#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
67fa8c25 HS	133	#define CONFIG_PHY_BASE_ADR 0
	134	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	135	#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
	136
	137	/*
	138	* UBI related stuff
	139	*/
	140	#define CONFIG_SYS_USE_UBI
	141
	142	/*
	143	* I2C related stuff
	144	*/
67fa8c25 HS	145	#define CONFIG_SOFT_I2C /* I2C bit-banged */
67fa8c25 HS	146
67fa8c25 HS	147	#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
	148	#if defined(CONFIG_SOFT_I2C)
	149	#ifndef __ASSEMBLY__
	150	#include <asm/arch-kirkwood/gpio.h>
	151	extern void __set_direction(unsigned pin, int high);
	152	void set_sda (int state);
	153	void set_scl (int state);
	154	int get_sda (void);
	155	int get_scl (void);
	156	#define SUEN3_SDA_PIN 8
	157	#define SUEN3_SCL_PIN 9
	158	#define SUEN3_ENV_WP 38
	159
	160	#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0)
	161	#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1)
	162	#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
	163	#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit);
	164	#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit);
	165	#endif
	166
	167	#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
	168	#define I2C_SOFT_DECLARATIONS
	169
	170	#define CONFIG_SYS_I2C_SLAVE 0x0
	171	#define CONFIG_SYS_I2C_SPEED 100000
	172	#endif
	173
	174	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	175	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	176
	177	#if defined(CONFIG_SYS_NO_FLASH)
	178	#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
	179	#undef CONFIG_FLASH_CFI_MTD
	180	#undef CONFIG_JFFS2_CMDLINE
	181	#endif
	182
a784c01a	183	/* additions for new relocation code, must be added to all boards */
ab86f72c HS	184	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	185	#define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \
	186	CONFIG_SYS_GBL_DATA_SIZE)
67fa8c25	187	#endif /* _CONFIG_KM_ARM_H */