]>
Commit | Line | Data |
---|---|---|
de044361 HS |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
6 | * Peter Barada <peterb@logicpd.com> | |
7 | * | |
8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
10 | * | |
f41ee960 | 11 | * (C) Copyright 2008-2011 |
de044361 HS |
12 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | */ | |
b11f53f3 HS |
26 | #define CONFIG_QE /* Has QE */ |
27 | #define CONFIG_MPC8360 /* MPC8360 CPU specific */ | |
28 | #define CONFIG_KMETER1 /* KMETER1 board specific */ | |
605f78e3 | 29 | #define CONFIG_HOSTNAME kmeter1 |
62ddcf05 | 30 | #define CONFIG_KM_BOARD_NAME "kmeter1" |
de044361 | 31 | |
2ae18241 | 32 | #define CONFIG_SYS_TEXT_BASE 0xF0000000 |
de3ad13d HB |
33 | #define CONFIG_KM_DEF_NETDEV \ |
34 | "netdev=eth2\0" \ | |
2ae18241 | 35 | |
62ddcf05 | 36 | /* include common defines/options for all 83xx Keymile boards */ |
264eaa0e | 37 | #include "km/km83xx-common.h" |
4897ee33 | 38 | |
b11f53f3 | 39 | #define CONFIG_MISC_INIT_R |
de044361 | 40 | /* |
62ddcf05 | 41 | * System IO Setup |
de044361 | 42 | */ |
62ddcf05 | 43 | #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) |
de044361 HS |
44 | |
45 | /* | |
46 | * Hardware Reset Configuration Word | |
47 | */ | |
48 | #define CONFIG_SYS_HRCW_LOW (\ | |
49 | HRCWL_CSB_TO_CLKIN_4X1 | \ | |
50 | HRCWL_CORE_TO_CSB_2X1 | \ | |
51 | HRCWL_CE_PLL_VCO_DIV_2 | \ | |
b43b12e6 | 52 | HRCWL_CE_TO_PLL_1X6) |
de044361 HS |
53 | |
54 | #define CONFIG_SYS_HRCW_HIGH (\ | |
55 | HRCWH_CORE_ENABLE | \ | |
56 | HRCWH_FROM_0X00000100 | \ | |
605f78e3 | 57 | HRCWH_BOOTSEQ_DISABLE | \ |
de044361 HS |
58 | HRCWH_SW_WATCHDOG_DISABLE | \ |
59 | HRCWH_ROM_LOC_LOCAL_16BIT | \ | |
60 | HRCWH_BIG_ENDIAN | \ | |
605f78e3 | 61 | HRCWH_LALE_EARLY | \ |
b43b12e6 | 62 | HRCWH_LDP_CLEAR) |
de044361 | 63 | |
118cbe3c | 64 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f |
de044361 HS |
65 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
66 | SDRAM_CFG_SREN) | |
67 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
68 | #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
605f78e3 HS |
69 | #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
70 | (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT)) | |
de044361 | 71 | |
62ddcf05 HS |
72 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
73 | CSCONFIG_ROW_BIT_13 | \ | |
74 | CSCONFIG_COL_BIT_10 | \ | |
75 | CSCONFIG_ODT_WR_ACS) | |
76 | ||
605f78e3 HS |
77 | #define CONFIG_SYS_DDRCDR 0x40000001 |
78 | #define CONFIG_SYS_DDR_MODE 0x47860452 | |
79 | #define CONFIG_SYS_DDR_MODE2 0x8080c000 | |
de044361 HS |
80 | |
81 | #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ | |
82 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ | |
83 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ | |
84 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ | |
85 | (0 << TIMING_CFG0_WWT_SHIFT) | \ | |
86 | (0 << TIMING_CFG0_RRT_SHIFT) | \ | |
87 | (0 << TIMING_CFG0_WRT_SHIFT) | \ | |
88 | (0 << TIMING_CFG0_RWT_SHIFT)) | |
89 | ||
b11f53f3 HS |
90 | #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ |
91 | (2 << TIMING_CFG1_WRTORD_SHIFT) | \ | |
92 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ | |
93 | (3 << TIMING_CFG1_WRREC_SHIFT) | \ | |
94 | (7 << TIMING_CFG1_REFREC_SHIFT) | \ | |
95 | (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ | |
96 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ | |
97 | (3 << TIMING_CFG1_PRETOACT_SHIFT)) | |
605f78e3 HS |
98 | |
99 | #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ | |
de044361 HS |
100 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
101 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ | |
605f78e3 HS |
102 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ |
103 | (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ | |
de044361 | 104 | (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ |
605f78e3 | 105 | (5 << TIMING_CFG2_CPO_SHIFT)) |
de044361 HS |
106 | |
107 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
108 | ||
8ed74341 HS |
109 | /* PRIO FPGA */ |
110 | #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 | |
111 | #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 | |
112 | /* PAXE FPGA */ | |
113 | #define CONFIG_SYS_PAXE_BASE 0xA0000000 | |
605f78e3 | 114 | #define CONFIG_SYS_PAXE_SIZE 512 |
de044361 | 115 | |
62ddcf05 HS |
116 | /* EEprom support */ |
117 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
de044361 HS |
118 | |
119 | /* | |
120 | * Local Bus Configuration & Clock Setup | |
121 | */ | |
c7190f02 KP |
122 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
123 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 | |
124 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
de044361 HS |
125 | |
126 | /* | |
127 | * Init Local Bus Memory Controller: | |
128 | * | |
129 | * Bank Bus Machine PortSz Size Device | |
130 | * ---- --- ------- ------ ----- ------ | |
605f78e3 | 131 | * 3 Local GPCM 8 bit 512MB PAXE |
de044361 HS |
132 | * |
133 | */ | |
de044361 HS |
134 | |
135 | /* | |
136 | * PAXE on the local bus CS3 | |
137 | */ | |
b11f53f3 | 138 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE |
605f78e3 | 139 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ |
de044361 HS |
140 | |
141 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ | |
142 | (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ | |
143 | BR_V) | |
144 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ | |
145 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ | |
146 | OR_GPCM_SCY_2 | \ | |
147 | OR_GPCM_TRLX | OR_GPCM_EAD) | |
148 | ||
de044361 HS |
149 | /* |
150 | * MMU Setup | |
151 | */ | |
152 | ||
de044361 | 153 | /* PAXE: icache cacheable, but dcache-inhibit and guarded */ |
72cd4087 | 154 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ |
62ddcf05 | 155 | BATL_MEMCOHERENCE) |
b11f53f3 | 156 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ |
62ddcf05 | 157 | BATU_VS | BATU_VP) |
72cd4087 | 158 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ |
de044361 HS |
159 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
160 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
161 | ||
162 | #ifdef CONFIG_PCI | |
163 | /* PCI MEM space: cacheable */ | |
72cd4087 | 164 | #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) |
de044361 HS |
165 | #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
166 | #define CFG_DBAT6L CFG_IBAT6L | |
167 | #define CFG_DBAT6U CFG_IBAT6U | |
168 | /* PCI MMIO space: cache-inhibit and guarded */ | |
72cd4087 | 169 | #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \ |
de044361 HS |
170 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
171 | #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
172 | #define CFG_DBAT7L CFG_IBAT7L | |
173 | #define CFG_DBAT7U CFG_IBAT7U | |
174 | #else /* CONFIG_PCI */ | |
175 | #define CONFIG_SYS_IBAT6L (0) | |
176 | #define CONFIG_SYS_IBAT6U (0) | |
177 | #define CONFIG_SYS_IBAT7L (0) | |
178 | #define CONFIG_SYS_IBAT7U (0) | |
179 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
180 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
181 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
182 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
183 | #endif /* CONFIG_PCI */ | |
184 | ||
de044361 | 185 | #endif /* __CONFIG_H */ |