[people/ms/u-boot.git] / include / configs / kzm9g.h

/*
 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __KZM9G_H
#define __KZM9G_H

#undef DEBUG

#define CONFIG_SYS_CACHELINE_SIZE	32

#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G

#include <asm/arch/rmobile.h>

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_CMD_BOOTZ

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
#define CONFIG_BOOTDELAY 3

#define CONFIG_VERSION_VARIABLE
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define KZM_SDRAM_BASE	(0x40000000)
#define PHYS_SDRAM		KZM_SDRAM_BASE
#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS	(1)

/* NOR Flash */
#define KZM_FLASH_BASE	(0x00000000)
#define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
#define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
#define CONFIG_SYS_MAX_FLASH_BANKS	(1)
#define CONFIG_SYS_MAX_FLASH_SECT	(512)

/* prompt */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF4
#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE

#define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END \
	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
#undef  CONFIG_SYS_ALT_MEMTEST
#undef  CONFIG_SYS_MEMTEST_SCRATCH
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
#define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

#define CONFIG_SYS_TEXT_BASE		0x00000000
#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
#define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
#define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_ENV_IS_IN_FLASH

/* GPIO / PFC */
#define CONFIG_SH_GPIO_PFC

/* Clock */
#define CONFIG_GLOBAL_TIMER
#define CONFIG_SYS_CLK_FREQ	(48000000)
#define CONFIG_SYS_CPU_CLK	(1196000000)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */

/* Ether */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	(0x10000000)
#define CONFIG_SMC911X_32_BIT
#define CONFIG_NFS_TIMEOUT 10000UL

/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
#define CONFIG_SYS_I2C_SH_SPEED0	100000
#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
#define CONFIG_SYS_I2C_SH_SPEED1	100000
#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
#define CONFIG_SYS_I2C_SH_SPEED2	100000
#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
#define CONFIG_SYS_I2C_SH_SPEED3	100000
#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
#define CONFIG_SYS_I2C_SH_SPEED4	100000
#define CONFIG_SH_I2C_8BIT
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW  5
#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */

#endif /* __KZM9G_H */
Commit	Line	Data
8d811ca3 NI	1	/*
	2	* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	3	* Copyright (C) 2012 Renesas Solutions Corp.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
8d811ca3 NI	6	*/
	7
	8	#ifndef __KZM9G_H
	9	#define __KZM9G_H
	10
	11	#undef DEBUG
	12
3709844f AA	13	#define CONFIG_SYS_CACHELINE_SIZE 32
3709844f AA	14
8d811ca3 NI	15	#define CONFIG_SH73A0
	16	#define CONFIG_KZM_A9_GT
	17	#define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
	18	#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
	19
	20	#include <asm/arch/rmobile.h>
	21
	22	#define CONFIG_ARCH_CPU_INIT
	23	#define CONFIG_DISPLAY_CPUINFO
	24	#define CONFIG_DISPLAY_BOARDINFO
	25	#define CONFIG_BOARD_EARLY_INIT_F
8d811ca3	26
8d811ca3 NI	27	#define CONFIG_CMDLINE_TAG
	28	#define CONFIG_SETUP_MEMORY_TAGS
	29	#define CONFIG_INITRD_TAG
	30	#define CONFIG_DOS_PARTITION
	31	#define CONFIG_CMD_FAT
	32	#define CONFIG_CMD_BOOTZ
	33
18a65af4	34	#define CONFIG_BAUDRATE 115200
8d811ca3	35	#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
8d811ca3 NI	36	#define CONFIG_BOOTDELAY 3
	37
	38	#define CONFIG_VERSION_VARIABLE
	39	#undef CONFIG_SHOW_BOOT_PROGRESS
	40
	41	/* MEMORY */
	42	#define KZM_SDRAM_BASE (0x40000000)
	43	#define PHYS_SDRAM KZM_SDRAM_BASE
	44	#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
	45	#define CONFIG_NR_DRAM_BANKS (1)
	46
	47	/* NOR Flash */
	48	#define KZM_FLASH_BASE (0x00000000)
	49	#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
	50	#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
	51	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	52	#define CONFIG_SYS_MAX_FLASH_SECT (512)
	53
	54	/* prompt */
	55	#define CONFIG_SYS_LONGHELP
8d811ca3 NI	56	#define CONFIG_SYS_CBSIZE 256
	57	#define CONFIG_SYS_PBSIZE 256
	58	#define CONFIG_SYS_MAXARGS 16
	59	#define CONFIG_SYS_BARGSIZE 512
	60	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	61
	62	/* SCIF */
	63	#define CONFIG_SCIF_CONSOLE
	64	#define CONFIG_CONS_SCIF4
	65	#undef CONFIG_SYS_CONSOLE_INFO_QUIET
	66	#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	67	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
	68
	69	#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
	70	#define CONFIG_SYS_MEMTEST_END \
	71	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
	72	#undef CONFIG_SYS_ALT_MEMTEST
	73	#undef CONFIG_SYS_MEMTEST_SCRATCH
	74	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	75
	76	#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
	77	#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
	78	#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
	79	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	80	CONFIG_SYS_INIT_RAM_SIZE - \
	81	GENERATED_GBL_DATA_SIZE)
9415cf93 TK	82	#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
	83	#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
	84	#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
8d811ca3 NI	85	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	86
	87	#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
	88	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
8d811ca3 NI	89	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	90
	91	#define CONFIG_SYS_TEXT_BASE 0x00000000
	92	#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
	93
	94	/* FLASH */
	95	#define CONFIG_FLASH_CFI_DRIVER
	96	#define CONFIG_SYS_FLASH_CFI
	97	#undef CONFIG_SYS_FLASH_QUIET_TEST
	98	#define CONFIG_SYS_FLASH_EMPTY_INFO
	99	#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
	100	#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
	101	#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
	102	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	103
	104	/* Timeout for Flash erase operations (in ms) */
	105	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	106	/* Timeout for Flash write operations (in ms) */
	107	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	108	/* Timeout for Flash set sector lock bit operations (in ms) */
	109	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	110	/* Timeout for Flash clear lock bit operations (in ms) */
	111	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	112
	113	#undef CONFIG_SYS_FLASH_PROTECTION
	114	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
	115	#define CONFIG_ENV_IS_IN_FLASH
	116
	117	/* GPIO / PFC */
	118	#define CONFIG_SH_GPIO_PFC
	119
	120	/* Clock */
eae6c8ab	121	#define CONFIG_GLOBAL_TIMER
8d811ca3 NI	122	#define CONFIG_SYS_CLK_FREQ (48000000)
8d811ca3 NI	123	#define CONFIG_SYS_CPU_CLK (1196000000)
59562ff6	124	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8d811ca3	125	#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
8d811ca3 NI	126
8d811ca3 NI	127	/* Ether */
8d811ca3 NI	128	#define CONFIG_CMD_PING
	129	#define CONFIG_CMD_DHCP
	130	#define CONFIG_SMC911X
	131	#define CONFIG_SMC911X_BASE (0x10000000)
	132	#define CONFIG_SMC911X_32_BIT
38263df8	133	#define CONFIG_NFS_TIMEOUT 10000UL
8d811ca3 NI	134
	135	/* I2C */
	136	#define CONFIG_CMD_I2C
2035d77d NI	137	#define CONFIG_SYS_I2C
	138	#define CONFIG_SYS_I2C_SH
	139	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
	140	#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
	141	#define CONFIG_SYS_I2C_SH_SPEED0 100000
	142	#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
	143	#define CONFIG_SYS_I2C_SH_SPEED1 100000
	144	#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
	145	#define CONFIG_SYS_I2C_SH_SPEED2 100000
	146	#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
	147	#define CONFIG_SYS_I2C_SH_SPEED3 100000
	148	#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
	149	#define CONFIG_SYS_I2C_SH_SPEED4 100000
b1af67fe	150	#define CONFIG_SH_I2C_8BIT
2035d77d NI	151	#define CONFIG_SH_I2C_DATA_HIGH 4
	152	#define CONFIG_SH_I2C_DATA_LOW 5
	153	#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
8d811ca3 NI	154
8d811ca3 NI	155	#endif /* __KZM9G_H */