[people/ms/u-boot.git] / include / configs / kzm9g.h

/*
 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __KZM9G_H
#define __KZM9G_H

#undef DEBUG

#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_ARCH_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G

#include <asm/arch/rmobile.h>

#define CONFIG_ARCH_CPU_INIT

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#undef  CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define KZM_SDRAM_BASE	(0x40000000)
#define PHYS_SDRAM		KZM_SDRAM_BASE
#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS	(1)

/* NOR Flash */
#define KZM_FLASH_BASE	(0x00000000)
#define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
#define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
#define CONFIG_SYS_MAX_FLASH_BANKS	(1)
#define CONFIG_SYS_MAX_FLASH_SECT	(512)

/* prompt */
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF4

#define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END \
	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
#undef  CONFIG_SYS_ALT_MEMTEST
#undef  CONFIG_SYS_MEMTEST_SCRATCH
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
#define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
#define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
#define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* GPIO / PFC */
#define CONFIG_SH_GPIO_PFC

/* Clock */
#define CONFIG_GLOBAL_TIMER
#define CONFIG_SYS_CLK_FREQ	(48000000)
#define CONFIG_SYS_CPU_CLK	(1196000000)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#define CONFIG_NFS_TIMEOUT 10000UL

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
#define CONFIG_SYS_I2C_SH_SPEED0	100000
#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
#define CONFIG_SYS_I2C_SH_SPEED1	100000
#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
#define CONFIG_SYS_I2C_SH_SPEED2	100000
#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
#define CONFIG_SYS_I2C_SH_SPEED3	100000
#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
#define CONFIG_SYS_I2C_SH_SPEED4	100000
#define CONFIG_SH_I2C_8BIT
#define CONFIG_SH_I2C_DATA_HIGH 4
#define CONFIG_SH_I2C_DATA_LOW  5
#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */

#endif /* __KZM9G_H */
Commit	Line	Data
8d811ca3 NI	1	/*
	2	* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	3	* Copyright (C) 2012 Renesas Solutions Corp.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
8d811ca3 NI	6	*/
	7
	8	#ifndef __KZM9G_H
	9	#define __KZM9G_H
	10
	11	#undef DEBUG
	12
8d811ca3 NI	13	#define CONFIG_SH73A0
8d811ca3 NI	14	#define CONFIG_KZM_A9_GT
1cc95f6e	15	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
8d811ca3 NI	16	#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
	17
	18	#include <asm/arch/rmobile.h>
	19
	20	#define CONFIG_ARCH_CPU_INIT
8d811ca3	21
8d811ca3 NI	22	#define CONFIG_CMDLINE_TAG
	23	#define CONFIG_SETUP_MEMORY_TAGS
	24	#define CONFIG_INITRD_TAG
8d811ca3	25
8d811ca3 NI	26	#undef CONFIG_SHOW_BOOT_PROGRESS
	27
	28	/* MEMORY */
	29	#define KZM_SDRAM_BASE (0x40000000)
	30	#define PHYS_SDRAM KZM_SDRAM_BASE
	31	#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
	32	#define CONFIG_NR_DRAM_BANKS (1)
	33
	34	/* NOR Flash */
	35	#define KZM_FLASH_BASE (0x00000000)
	36	#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
	37	#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
	38	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	39	#define CONFIG_SYS_MAX_FLASH_SECT (512)
	40
	41	/* prompt */
8d811ca3	42	#define CONFIG_SYS_PBSIZE 256
8d811ca3 NI	43	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	44
	45	/* SCIF */
8d811ca3	46	#define CONFIG_CONS_SCIF4
8d811ca3 NI	47
	48	#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
	49	#define CONFIG_SYS_MEMTEST_END \
	50	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
	51	#undef CONFIG_SYS_ALT_MEMTEST
	52	#undef CONFIG_SYS_MEMTEST_SCRATCH
	53	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	54
	55	#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
	56	#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
	57	#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
	58	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	59	CONFIG_SYS_INIT_RAM_SIZE - \
	60	GENERATED_GBL_DATA_SIZE)
9415cf93 TK	61	#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
	62	#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
	63	#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
8d811ca3 NI	64	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
	65
	66	#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
	67	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
8d811ca3 NI	68	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
8d811ca3 NI	69
8d811ca3 NI	70	#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
	71
	72	/* FLASH */
	73	#define CONFIG_FLASH_CFI_DRIVER
	74	#define CONFIG_SYS_FLASH_CFI
	75	#undef CONFIG_SYS_FLASH_QUIET_TEST
	76	#define CONFIG_SYS_FLASH_EMPTY_INFO
	77	#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
	78	#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
	79	#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
	80	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	81
	82	/* Timeout for Flash erase operations (in ms) */
	83	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	84	/* Timeout for Flash write operations (in ms) */
	85	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	86	/* Timeout for Flash set sector lock bit operations (in ms) */
	87	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	88	/* Timeout for Flash clear lock bit operations (in ms) */
	89	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	90
	91	#undef CONFIG_SYS_FLASH_PROTECTION
	92	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
8d811ca3 NI	93
	94	/* GPIO / PFC */
	95	#define CONFIG_SH_GPIO_PFC
	96
	97	/* Clock */
eae6c8ab	98	#define CONFIG_GLOBAL_TIMER
8d811ca3 NI	99	#define CONFIG_SYS_CLK_FREQ (48000000)
8d811ca3 NI	100	#define CONFIG_SYS_CPU_CLK (1196000000)
59562ff6	101	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8d811ca3	102	#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
8d811ca3	103
38263df8	104	#define CONFIG_NFS_TIMEOUT 10000UL
8d811ca3 NI	105
8d811ca3 NI	106	/* I2C */
2035d77d NI	107	#define CONFIG_SYS_I2C
	108	#define CONFIG_SYS_I2C_SH
	109	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
	110	#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
	111	#define CONFIG_SYS_I2C_SH_SPEED0 100000
	112	#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
	113	#define CONFIG_SYS_I2C_SH_SPEED1 100000
	114	#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
	115	#define CONFIG_SYS_I2C_SH_SPEED2 100000
	116	#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
	117	#define CONFIG_SYS_I2C_SH_SPEED3 100000
	118	#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
	119	#define CONFIG_SYS_I2C_SH_SPEED4 100000
b1af67fe	120	#define CONFIG_SH_I2C_8BIT
2035d77d NI	121	#define CONFIG_SH_I2C_DATA_HIGH 4
	122	#define CONFIG_SH_I2C_DATA_LOW 5
	123	#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
8d811ca3 NI	124
8d811ca3 NI	125	#endif /* __KZM9G_H */