[people/ms/u-boot.git] / include / configs / lager.h

/*
 * include/configs/lager.h
 *     This file is lager board configuration.
 *
 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __LAGER_H
#define __LAGER_H

#undef DEBUG
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"

#include "rcar-gen2-common.h"

/* STACK */
#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK	\
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */

/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_RCAR
#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)

#define CONFIG_SYS_TMU_CLK_DIV	4

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	3

/* MMC */
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR		0xEE220000
#define CONFIG_SH_MMCIF_CLK		97500000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA	0x00200000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ	97500000

#endif	/* __LAGER_H */
Commit	Line	Data
f4ec4522 NI	1	/*
	2	* include/configs/lager.h
	3	* This file is lager board configuration.
	4	*
5ca6dfe6	5	* Copyright (C) 2013, 2014 Renesas Electronics Corporation
f4ec4522 NI	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#ifndef __LAGER_H
	11	#define __LAGER_H
	12
	13	#undef DEBUG
1cc95f6e	14	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
f4ec4522	15
5ca6dfe6	16	#include "rcar-gen2-common.h"
d80149b2	17
f4ec4522	18	/* STACK */
fb6f6001 NI	19	#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
	20	#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
	21	#else
	22	#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
	23	#endif
	24	#define STACK_AREA_SIZE 0xC000
f4ec4522 NI	25	#define LOW_LEVEL_MERAM_STACK \
	26	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	27
	28	/* MEMORY */
5ca6dfe6 NI	29	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	30	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	31	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
f4ec4522 NI	32
f4ec4522 NI	33	/* SCIF */
f4ec4522	34
5ca6dfe6	35	/* SPI */
0e05b217	36	#define CONFIG_SPI
0e05b217	37	#define CONFIG_SH_QSPI
0e05b217	38
23565c6b	39	/* SH Ether */
23565c6b NI	40	#define CONFIG_SH_ETHER_USE_PORT 0
	41	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	42	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	43	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	44	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	45	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
23565c6b NI	46	#define CONFIG_BITBANGMII
	47	#define CONFIG_BITBANGMII_MULTI
	48
b9107adf NI	49	/* I2C */
	50	#define CONFIG_SYS_I2C
	51	#define CONFIG_SYS_I2C_RCAR
b9107adf	52	#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
b9107adf	53	#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
b9107adf	54	#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
b9107adf NI	55	#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
	56	#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
	57
b9986be0 NI	58	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
b9986be0 NI	59
f4ec4522	60	/* Board Clock */
b1f78a2e NI	61	#define RMOBILE_XTAL_CLK 20000000u
	62	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	63	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	64	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
f4ec4522 NI	65	#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
f4ec4522 NI	66	#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
b9107adf	67	#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
f4ec4522 NI	68
f4ec4522 NI	69	#define CONFIG_SYS_TMU_CLK_DIV 4
f4ec4522	70
5c4bb96e	71	/* USB */
5c4bb96e	72	#define CONFIG_USB_EHCI_RMOBILE
5906fade	73	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
5c4bb96e	74
d7916b1d	75	/* MMC */
d7916b1d NI	76	#define CONFIG_SH_MMCIF
	77	#define CONFIG_SH_MMCIF_ADDR 0xEE220000
	78	#define CONFIG_SH_MMCIF_CLK 97500000
	79
8e2e5886 NI	80	/* Module stop status bits */
	81	/* INTC-RT */
	82	#define CONFIG_SMSTP0_ENA 0x00400000
	83	/* MSIF */
	84	#define CONFIG_SMSTP2_ENA 0x00002000
	85	/* INTC-SYS, IRQC */
	86	#define CONFIG_SMSTP4_ENA 0x00000180
	87	/* SCIF0 */
	88	#define CONFIG_SMSTP7_ENA 0x00200000
	89
acdfecbb NI	90	/* SDHI */
	91	#define CONFIG_SH_SDHI_FREQ 97500000
	92
f4ec4522	93	#endif /* __LAGER_H */