projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f4ec4522 NI |
1 | /* |
| 2 | * include/configs/lager.h | |
| 3 | * This file is lager board configuration. | |
| 4 | * | |
| 5ca6dfe6 | 5 | * Copyright (C) 2013, 2014 Renesas Electronics Corporation |
| f4ec4522 NI |
6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0 | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef __LAGER_H | |
| 11 | #define __LAGER_H | |
| 12 | ||
| 13 | #undef DEBUG | |
| f4ec4522 | 14 | #define CONFIG_R8A7790 |
| 1cc95f6e | 15 | #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager" |
| f4ec4522 | 16 | |
| 5ca6dfe6 | 17 | #include "rcar-gen2-common.h" |
| d80149b2 | 18 | |
| 1cc95f6e | 19 | #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) |
| fb6f6001 NI |
20 | #define CONFIG_SYS_TEXT_BASE 0xB0000000 |
| 21 | #else | |
| 0e05b217 | 22 | #define CONFIG_SYS_TEXT_BASE 0xE8080000 |
| fb6f6001 | 23 | #endif |
| f4ec4522 NI |
24 | |
| 25 | /* STACK */ | |
| fb6f6001 NI |
26 | #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) |
| 27 | #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC | |
| 28 | #else | |
| 29 | #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC | |
| 30 | #endif | |
| 31 | #define STACK_AREA_SIZE 0xC000 | |
| f4ec4522 NI |
32 | #define LOW_LEVEL_MERAM_STACK \ |
| 33 | (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) | |
| 34 | ||
| 35 | /* MEMORY */ | |
| 5ca6dfe6 NI |
36 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 |
| 37 | #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) | |
| 38 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) | |
| f4ec4522 NI |
39 | |
| 40 | /* SCIF */ | |
| f4ec4522 | 41 | |
| 5ca6dfe6 | 42 | /* SPI */ |
| 0e05b217 | 43 | #define CONFIG_SPI |
| 0e05b217 | 44 | #define CONFIG_SH_QSPI |
| 0e05b217 | 45 | |
| 23565c6b | 46 | /* SH Ether */ |
| 23565c6b NI |
47 | #define CONFIG_SH_ETHER |
| 48 | #define CONFIG_SH_ETHER_USE_PORT 0 | |
| 49 | #define CONFIG_SH_ETHER_PHY_ADDR 0x1 | |
| 50 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII | |
| 51 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 | |
| 52 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK | |
| 53 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE | |
| 23565c6b NI |
54 | #define CONFIG_PHY_MICREL |
| 55 | #define CONFIG_BITBANGMII | |
| 56 | #define CONFIG_BITBANGMII_MULTI | |
| 57 | ||
| b9107adf NI |
58 | /* I2C */ |
| 59 | #define CONFIG_SYS_I2C | |
| 60 | #define CONFIG_SYS_I2C_RCAR | |
| b9107adf | 61 | #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 |
| b9107adf | 62 | #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 |
| b9107adf | 63 | #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 |
| b9107adf NI |
64 | #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 |
| 65 | #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 | |
| 66 | ||
| b9986be0 NI |
67 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ |
| 68 | ||
| f4ec4522 | 69 | /* Board Clock */ |
| b1f78a2e NI |
70 | #define RMOBILE_XTAL_CLK 20000000u |
| 71 | #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK | |
| 72 | #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ | |
| 73 | #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) | |
| f4ec4522 NI |
74 | #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) |
| 75 | #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) | |
| b9107adf | 76 | #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) |
| f4ec4522 NI |
77 | |
| 78 | #define CONFIG_SYS_TMU_CLK_DIV 4 | |
| f4ec4522 | 79 | |
| 5c4bb96e | 80 | /* USB */ |
| 5c4bb96e | 81 | #define CONFIG_USB_EHCI_RMOBILE |
| 5906fade | 82 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
| 5c4bb96e | 83 | |
| d7916b1d | 84 | /* MMC */ |
| d7916b1d NI |
85 | #define CONFIG_SH_MMCIF |
| 86 | #define CONFIG_SH_MMCIF_ADDR 0xEE220000 | |
| 87 | #define CONFIG_SH_MMCIF_CLK 97500000 | |
| 88 | ||
| 8e2e5886 NI |
89 | /* Module stop status bits */ |
| 90 | /* INTC-RT */ | |
| 91 | #define CONFIG_SMSTP0_ENA 0x00400000 | |
| 92 | /* MSIF */ | |
| 93 | #define CONFIG_SMSTP2_ENA 0x00002000 | |
| 94 | /* INTC-SYS, IRQC */ | |
| 95 | #define CONFIG_SMSTP4_ENA 0x00000180 | |
| 96 | /* SCIF0 */ | |
| 97 | #define CONFIG_SMSTP7_ENA 0x00200000 | |
| 98 | ||
| acdfecbb NI |
99 | /* SDHI */ |
| 100 | #define CONFIG_SH_SDHI_FREQ 97500000 | |
| 101 | ||
| f4ec4522 | 102 | #endif /* __LAGER_H */ |