[people/ms/u-boot.git] / include / configs / lager.h

/*
 * include/configs/lager.h
 *     This file is lager board configuration.
 *
 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __LAGER_H
#define __LAGER_H

#undef DEBUG
#define CONFIG_R8A7790
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0xB0000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE8080000
#endif

/* STACK */
#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK	\
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */
#define CONFIG_SCIF_CONSOLE

/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_RCAR
#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)

#define CONFIG_SYS_TMU_CLK_DIV	4

/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	3

/* MMC */
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR		0xEE220000
#define CONFIG_SH_MMCIF_CLK		97500000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA	0x00200000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ	97500000

#endif	/* __LAGER_H */
Commit	Line	Data
f4ec4522 NI	1	/*
	2	* include/configs/lager.h
	3	* This file is lager board configuration.
	4	*
5ca6dfe6	5	* Copyright (C) 2013, 2014 Renesas Electronics Corporation
f4ec4522 NI	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#ifndef __LAGER_H
	11	#define __LAGER_H
	12
	13	#undef DEBUG
f4ec4522	14	#define CONFIG_R8A7790
1cc95f6e	15	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
f4ec4522	16
5ca6dfe6	17	#include "rcar-gen2-common.h"
d80149b2	18
1cc95f6e	19	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
fb6f6001 NI	20	#define CONFIG_SYS_TEXT_BASE 0xB0000000
fb6f6001 NI	21	#else
0e05b217	22	#define CONFIG_SYS_TEXT_BASE 0xE8080000
fb6f6001	23	#endif
f4ec4522 NI	24
f4ec4522 NI	25	/* STACK */
fb6f6001 NI	26	#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
	27	#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
	28	#else
	29	#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
	30	#endif
	31	#define STACK_AREA_SIZE 0xC000
f4ec4522 NI	32	#define LOW_LEVEL_MERAM_STACK \
	33	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	34
	35	/* MEMORY */
5ca6dfe6 NI	36	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	37	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	38	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
f4ec4522 NI	39
	40	/* SCIF */
	41	#define CONFIG_SCIF_CONSOLE
f4ec4522	42
5ca6dfe6	43	/* SPI */
0e05b217	44	#define CONFIG_SPI
0e05b217	45	#define CONFIG_SH_QSPI
0e05b217	46
23565c6b	47	/* SH Ether */
23565c6b NI	48	#define CONFIG_SH_ETHER
	49	#define CONFIG_SH_ETHER_USE_PORT 0
	50	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	51	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	52	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	53	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	54	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	55	#define CONFIG_PHYLIB
	56	#define CONFIG_PHY_MICREL
	57	#define CONFIG_BITBANGMII
	58	#define CONFIG_BITBANGMII_MULTI
	59
b9107adf NI	60	/* I2C */
	61	#define CONFIG_SYS_I2C
	62	#define CONFIG_SYS_I2C_RCAR
b9107adf	63	#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
b9107adf	64	#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
b9107adf	65	#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
b9107adf NI	66	#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
	67	#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
	68
b9986be0 NI	69	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
b9986be0 NI	70
f4ec4522	71	/* Board Clock */
b1f78a2e NI	72	#define RMOBILE_XTAL_CLK 20000000u
	73	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	74	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	75	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
f4ec4522 NI	76	#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
f4ec4522 NI	77	#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
b9107adf	78	#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
f4ec4522 NI	79
f4ec4522 NI	80	#define CONFIG_SYS_TMU_CLK_DIV 4
f4ec4522	81
5c4bb96e NI	82	/* USB */
	83	#define CONFIG_USB_EHCI
	84	#define CONFIG_USB_EHCI_RMOBILE
5906fade	85	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
5c4bb96e	86
d7916b1d	87	/* MMC */
d7916b1d NI	88	#define CONFIG_SH_MMCIF
	89	#define CONFIG_SH_MMCIF_ADDR 0xEE220000
	90	#define CONFIG_SH_MMCIF_CLK 97500000
	91
8e2e5886 NI	92	/* Module stop status bits */
	93	/* INTC-RT */
	94	#define CONFIG_SMSTP0_ENA 0x00400000
	95	/* MSIF */
	96	#define CONFIG_SMSTP2_ENA 0x00002000
	97	/* INTC-SYS, IRQC */
	98	#define CONFIG_SMSTP4_ENA 0x00000180
	99	/* SCIF0 */
	100	#define CONFIG_SMSTP7_ENA 0x00200000
	101
acdfecbb NI	102	/* SDHI */
	103	#define CONFIG_SH_SDHI_FREQ 97500000
	104
f4ec4522	105	#endif /* __LAGER_H */