]>
Commit | Line | Data |
---|---|---|
2ac07f75 DL |
1 | /* |
2 | * Copyright (C) 2016 David Lechner <david@lechnology.com> | |
3 | * | |
4 | * Based on da850evm.h | |
5 | * | |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
7 | * | |
8 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
9 | * | |
10 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
11 | * | |
12 | * SPDX-License-Identifier: GPL-2.0+ | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * SoC Configuration | |
20 | */ | |
21 | #define CONFIG_MACH_DAVINCI_DA850_EVM | |
22 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ | |
23 | #define CONFIG_SOC_DA850 /* TI DA850 SoC */ | |
24 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH | |
25 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
26 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
27 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
28 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
29 | #define CONFIG_SYS_DA850_PLL_INIT | |
30 | #define CONFIG_SYS_DA850_DDR_INIT | |
31 | ||
32 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
33 | ||
2ac07f75 DL |
34 | /* |
35 | * Memory Info | |
36 | */ | |
37 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
38 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
39 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
40 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
41 | ||
42 | /* memtest start addr */ | |
43 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
44 | ||
45 | /* memtest will be run on 16MB */ | |
46 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
47 | ||
48 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
49 | ||
50 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
51 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
52 | DAVINCI_SYSCFG_SUSPSRC_SPI0 | \ | |
53 | DAVINCI_SYSCFG_SUSPSRC_UART1 | \ | |
54 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
55 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
56 | ||
57 | /* | |
58 | * PLL configuration | |
59 | */ | |
60 | #define CONFIG_SYS_DV_CLKMODE 0 | |
61 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
62 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
63 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
64 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
65 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
66 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
67 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
68 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
69 | ||
70 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
71 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
72 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
73 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 | |
74 | ||
75 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
76 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
77 | ||
78 | /* | |
79 | * DDR2 memory configuration | |
80 | */ | |
81 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
82 | DV_DDR_PHY_EXT_STRBEN | \ | |
83 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
84 | ||
85 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
86 | (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ | |
87 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
88 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
89 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
90 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
91 | (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
92 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
93 | ||
94 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
95 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
96 | ||
97 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
98 | (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
99 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
100 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
101 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
102 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
103 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
104 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
105 | (0 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
106 | ||
107 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
108 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
109 | (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
110 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
111 | (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
112 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
113 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
114 | (0 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
115 | ||
116 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 | |
117 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
118 | ||
119 | /* | |
120 | * Serial Driver info | |
121 | */ | |
122 | #define CONFIG_SYS_NS16550_SERIAL | |
123 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
124 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ | |
125 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
126 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
127 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
128 | ||
129 | #define CONFIG_SPI | |
2ac07f75 DL |
130 | #define CONFIG_DAVINCI_SPI |
131 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE | |
132 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) | |
133 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
134 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
135 | ||
136 | /* | |
137 | * I2C Configuration | |
138 | */ | |
139 | #define CONFIG_SYS_I2C | |
140 | #define CONFIG_SYS_I2C_DAVINCI | |
141 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 | |
142 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
143 | ||
144 | /* | |
145 | * U-Boot general configuration | |
146 | */ | |
147 | #define CONFIG_BOARD_EARLY_INIT_F | |
148 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
149 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
150 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
151 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
152 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
153 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
2ac07f75 | 154 | #define CONFIG_AUTO_COMPLETE |
2ac07f75 DL |
155 | #define CONFIG_CMDLINE_EDITING |
156 | #define CONFIG_SYS_LONGHELP | |
157 | #define CONFIG_CRC32_VERIFY | |
158 | #define CONFIG_MX_CYCLIC | |
2ac07f75 DL |
159 | |
160 | /* | |
161 | * Linux Information | |
162 | */ | |
163 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
164 | #define CONFIG_HWCONFIG /* enable hwconfig */ | |
165 | #define CONFIG_CMDLINE_TAG | |
166 | #define CONFIG_REVISION_TAG | |
167 | #define CONFIG_SERIAL_TAG | |
168 | #define CONFIG_SETUP_MEMORY_TAGS | |
169 | #define CONFIG_SETUP_INITRD_TAG | |
2ac07f75 DL |
170 | #define CONFIG_BOOTCOMMAND \ |
171 | "if mmc rescan; then " \ | |
172 | "if run loadbootscr; then " \ | |
173 | "run bootscript; " \ | |
174 | "else " \ | |
175 | "if run loadimage; then " \ | |
176 | "run mmcargs; " \ | |
177 | "run mmcboot; " \ | |
178 | "else " \ | |
179 | "run flashargs; " \ | |
180 | "run flashboot; " \ | |
181 | "fi; " \ | |
182 | "fi; " \ | |
183 | "else " \ | |
184 | "run flashargs; " \ | |
185 | "run flashboot; " \ | |
186 | "fi" | |
187 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
188 | "hostname=EV3\0" \ | |
189 | "memsize=64M\0" \ | |
190 | "filesyssize=10M\0" \ | |
191 | "verify=n\0" \ | |
192 | "console=ttyS1,115200n8\0" \ | |
193 | "bootscraddr=0xC0600000\0" \ | |
194 | "loadaddr=0xC0007FC0\0" \ | |
195 | "filesysaddr=0xC1180000\0" \ | |
196 | "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ | |
197 | "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \ | |
198 | "mmcboot=bootm ${loadaddr}\0" \ | |
199 | "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \ | |
200 | "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \ | |
201 | "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ | |
202 | "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ | |
203 | "bootscript=source ${bootscraddr}\0" \ | |
204 | ||
205 | /* | |
206 | * U-Boot commands | |
207 | */ | |
2ac07f75 | 208 | #define CONFIG_CMD_DIAG |
2ac07f75 DL |
209 | #define CONFIG_CMD_SAVES |
210 | ||
211 | #ifdef CONFIG_CMD_BDI | |
212 | #define CONFIG_CLOCKS | |
213 | #endif | |
214 | ||
2ac07f75 DL |
215 | #define CONFIG_ENV_IS_NOWHERE |
216 | #define CONFIG_SYS_NO_FLASH | |
217 | #define CONFIG_ENV_SIZE (16 << 10) | |
218 | ||
219 | /* SD/MMC configuration */ | |
220 | #define CONFIG_MMC | |
221 | #define CONFIG_DAVINCI_MMC_SD1 | |
222 | #define CONFIG_GENERIC_MMC | |
223 | #define CONFIG_DAVINCI_MMC | |
224 | ||
225 | /* | |
226 | * Enable MMC commands only when | |
227 | * MMC support is present | |
228 | */ | |
229 | #ifdef CONFIG_MMC | |
230 | #define CONFIG_DOS_PARTITION | |
2ac07f75 DL |
231 | #endif |
232 | ||
233 | /* additions for new relocation code, must added to all boards */ | |
234 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
235 | ||
236 | #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 | |
237 | ||
238 | #endif /* __CONFIG_H */ |